Avalon总线规范详解

需积分: 10 102 浏览量更新于2024-08-02 收藏 2.2MB PDF 举报

Avalon Bus Specification 是一个专为Altera公司设计的高速系统级互连标准，它提供了一种高效、低延迟的数据传输机制，适用于高性能数字信号处理（DSP）、嵌入式系统和FPGA（Field-Programmable Gate Array）应用。这份参考手册详细阐述了Avalon总线架构，包括其设计理念、特性、接口规范以及使用该总线进行通信的方法。 1. **概述**: Avalon Bus Specification 版本2.3是在2003年7月发布的，旨在提升系统集成的效率和灵活性。它允许不同的硬件组件之间实现无缝的数据流传输，特别适合那些对带宽需求高、性能要求严格的实时应用。 2. **设计目标**: 该规格强调了高性能和低开销，通过减少数据总线上的信号宽度和数量，降低了信号线的数量和复杂性，从而减少了设计的复杂性和成本。这使得系统设计师能够更轻松地构建具有高性能和低功耗的系统。 3. **架构**: Avalon总线采用模块化设计，支持多种子类型，如Avalon-MM (Memory Mapped)用于主存访问，Avalon-ST (Streamlined Transfer)用于高速数据流传输，以及Avalon-DR (DMA)用于直接内存访问。这种细分提供了针对不同应用场景的最佳性能优化。 4. **接口**: 标准化了地址、数据和控制信号，使得连接到Avalon总线的设备可以遵循相同的交互模式，简化了系统集成。同时，它支持猝发传输、同步和异步操作，增强了与不同类型处理器和外设的兼容性。 5. **性能特点**: Avalon Bus通过使用分时复用的总线技术，提高了带宽利用效率，减少了总线争用，从而提升了系统吞吐量。它还支持可配置的数据宽度，根据实际需求动态调整，进一步提升了灵活性。 6. **版权和保障**: 所有内容受Altera Corporation的版权保护，未经许可不得复制或修改。用户在使用Avalon Bus时应遵守Altera的标准保修政策，但Altera保留在任何时候对产品和服务进行更改的权利。 7. **法律声明**: 使用Avalon Bus时需注意，除非另有注明，否则商标、服务标志、特定设备设计名称以及其他标识均为Altera的注册商标或服务标记，在美国和其他国家享有法律保护。任何其他产品或服务名称均属于各自所有者。总结来说，Avalon Bus Specification是Altera为高性能计算环境提供的一种高级互连标准，它通过优化数据传输、降低开销并支持多种数据传输模式，显著改善了系统设计的效率和灵活性。对于使用Altera FPGA的开发者来说，理解和掌握这一规格对于实现高效和兼容的系统至关重要。

16 Altera Corporation

Avalon Bus Specification Avalon Bus Specification Reference Manual

Avalon Peripherals

An Avalon peripheral on the Avalon bus is a logical device—either

on-chip or off-chip—that performs some system-level task, and

communicates with other system components through the Avalon

bus. Peripherals are modular system components, and may be added

or removed at design time, depending on the requirements of the

system.

Avalon peripherals can be memories and processors, as well as

traditional peripheral components, such as a UART, PIO, timer or

bus bridge. Any user logic can also be an Avalon peripheral, as long

as it provides address, data and control signal interfaces to the

Avalon bus as described in this document. A peripheral connects to

specific ports on the Avalon bus module allocated for that

peripheral. The peripheral may also have user-defined ports in

addition to the Avalon address, data and control signals. These

signals connect to custom logic external to the system module.

The roles of Avalon peripherals are classified as either a master or

slave. A master peripheral is a peripheral that can initiate bus

transfers on the Avalon bus. A master peripheral has at least one

master port (“Master Port” on page 17) which connects to the Avalon

bus module. A master peripheral may also have a slave port (“Slave

Port” on page 18), which allows the peripheral to receive bus

transfers initiated by other master peripherals on the Avalon bus. A

slave peripheral is a peripheral that only accepts bus transfers from

the Avalon bus, and cannot initiate bus transfers. Slave peripherals,

such as memory devices or UARTs, usually have only one slave port,

which connects to the Avalon bus module.

In the SOPC environment, it is important to make the distinction

between the following types of peripherals, which may be either

Avalon bus masters or slaves.

Altera Corporation 17

Avalon Bus Specification Reference Manual Avalon Bus Specification

Peripherals inside the System Module

If SOPC Builder finds a peripheral in a peripheral library, or if the

designer specifies the location of a custom peripheral design file,

then SOPC Builder automatically connects the peripheral to the

Avalon bus module. Such a peripheral is referred to as a peripheral

inside the system module, and is treated as a piece of the system

module. The details of connecting the address, data and control ports

to the Avalon bus module are hidden from the user. Any additional

non-Avalon ports on the peripheral are presented to the outside

world as ports on the system module. These ports may connect

directly to physical device pins, or may connect to the ports of other

on-chip modules.

Peripherals outside the System Module

An Avalon bus peripheral can also exist external to the system

module. This peripheral is referred to as a peripheral outside the

system module. A designer may chose to leave the module outside

the system module for several reasons:

■ The peripheral may exist physically outside the PLD.

■ The peripheral may require some glue logic to connect it to the

Avalon bus signals.

■ The peripheral design may not be complete at the time the

system module is generated.

In this case, the appropriate Avalon bus module signals are

presented to the outside world (and to the specific peripheral) as

ports on the system module.

Master Port

A master port is the collection of ports on a master peripheral used

to initiate transfers on the Avalon bus. The master port connects

directly to the Avalon bus module. In practice, a master peripheral

may have one or more master ports, as well as a slave port. The

interdependence of these master and slave ports is dependent on the

peripheral design. However, individual bus transfers on these

master or slave ports always conform to this document. Throughout

this document, a master transfer refers to an Avalon bus transfer

from the perspective of a single master port.

18 Altera Corporation

Avalon Bus Specification Avalon Bus Specification Reference Manual

Slave Port

A slave port is the collection of ports on a peripheral to accept Avalon

bus transfers from the master port on another Avalon peripheral.

The slave port connects directly to the Avalon bus module. Master

peripherals may also have a slave port, which allows the peripheral

to accept transfers from other masters on the Avalon bus.

Throughout this document, a slave transfer refers to an Avalon bus

transfer from the perspective of a single slave port.

Master-Slave Pair

A master-slave pair is the combination of a master port and a slave

port that are connected via the Avalon bus module. Structurally,

these master and slave ports connect to their appropriate ports on the

Avalon bus module. Effectively, the master port’s control and data

signals pass through the Avalon bus module, and interact with the

slave port. Connections between master and slave ports (thus

creating master-slave pairs) are specified in SOPC Builder.

PTF File & SOPC Builder Parameters & Switches

The configuration of the Avalon bus and peripherals can be specified

using the wizard-based SOPC Builder graphical user interface (GUI).

Through this GUI the user specifies various parameters and

switches, which are then used to generate a system PTF file. The PTF

file is a text file that fully defines:

■ Parameters that define the structure and/or functionality of the

Avalon bus module.

■ Parameters for each peripheral that define its structure and/or

functionality.

■ The master/slave role of each peripheral.

■ The ports (such as read enable, read data, write enable, write

data) present on each peripheral.

■ The arbitration mechanism for each slave port that can be

accessed by multiple master ports.

The PTF file is then passed to an HDL generator that creates the

actual register transfer level (RTL) description of the system module.

See the SOPC Builder Data Sheet and the SOPC Builder PTF File

Reference Manual for additional information about the system PTF

files.

Altera Corporation 19

Avalon Bus Specification Reference Manual Avalon Bus Specification

Avalon Bus

Transfers

The Avalon bus specification defines the signals and timing required

to transfer data between a master port and a slave port via the

Avalon bus module. The signals that comprise the interface between

the Avalon bus module and the peripheral are different, depending

on the type of transfer. Foremost, the interface is different for master

transfers and slave transfers, giving rise to the distinct definitions of

a slave port and a master port. Furthermore, the exact type and

number of signals required will vary, based on assignments made in

the system PTF file.

The Avalon bus specification offers a variety of options to tailor the

bus signals and timing to the needs of different types of peripherals.

Fundamental Avalon bus transfers move a single unit of data per bus

transfer between a master-slave pair. The bus transfer can be

extended with wait states to accommodate slow peripherals.

Streaming transactions along with simultaneous multi-master

capabilities accommodate high-bandwidth peripherals. Peripherals

can also use a combination of transaction types. The sequencing of

signals for all Avalon slave transfers are derived from the

fundamental slave read transfer and fundamental slave write

transfer. Likewise, the fundamental master read and master write

transfers are the basis for all Avalon master transfers.

Master Interface versus Slave Interface

When discussing Avalon bus transfers, it is important to pay

attention to which side of the bus is the focus: the master port

interface or the slave port interface. The signals output from a master

port on the Avalon bus module may be very different from the

corresponding signals that are input into the slave port on the target

peripheral.

The signal activity on the slave side is always the result of a master

peripheral initiating a bus transfer, but the actual slave port input

signals do not come directly from the master port. The Avalon bus

module relays the signals from the master port, and custom-tailors

the signals (e.g., inserts wait states; arbitrates between contending

masters) to the needs of the slave peripheral.

For this reason, the discussion of Avalon bus transfers is separated

into master transfer types and slave transfer types. Most designers

will be interested only in slave transfers, because the custom

peripherals they design (if any) will most likely be slave peripherals.

In this case, the designer considers only the signaling between the

Avalon bus module and the custom peripheral. The discussion of

master transfers is only relevant in the event that a designer creates

a master peripheral.

20 Altera Corporation

Avalon Bus Specification Avalon Bus Specification Reference Manual

Avalon Bus Timing

The Avalon bus is a synchronous bus interface, clocked by a master

Avalon bus clock. All bus transfers occur synchronous to the Avalon

bus clock. All bus transfers initiate on a rising clock edge, and

terminate after valid data is captured on (or before) a subsequent

rising clock edge.

A synchronous bus interface does not necessarily mean that all

Avalon bus signals are registered. Notably, the Avalon chipselect

signal is combinatorial, based on the outputs of registers that are

synchronous to the Avalon bus clock, clk. Therefore, peripherals

must not be edge sensitive to Avalon signals, because Avalon signals

may transition multiple times before they stabilize. As with any

synchronous design, Avalon bus peripherals must function only in

response to signals that are stable at the rising edge of clk, and

output stable signals at the rising edge of clk.

It is possible to interface asynchronous peripherals such as off-chip,

asynchronous memory to the Avalon bus module, but there are a few

design considerations. Due to the synchronous operation of the

Avalon bus module, Avalon signals toggle only at intervals equal to

the period of the Avalon bus clock. Also, if an asynchronous

peripheral’s outputs are connected directly to the Avalon bus

module, the designer must make sure that the output signals are

stable before the rising edge of clk.

The Avalon bus specification makes no attempt to dictate how

signals transition between clock edges. Toggling signals are

triggered by the Avalon bus clock, and that signals must stabilize

before the clock edge when they are captured. For this reason, the

Avalon bus timing diagrams in this document are devoid of explicit

timing information. The exact timing of signals toggling and

stabilizing between clock edges will vary, depending upon the

characteristics of the Altera PLD selected to implement the system.

By the same token, there is no inherent maximum performance of the

Avalon bus. After synthesis and place-and-route of the system

module for a specific device, the designer must perform standard

timing analysis on the system module to determine the maximum

speed at which Avalon bus transfers can be performed.

剩余105页未读，继续阅读

fcc124

粉丝: 0
资源: 2

Avalon总线规范详解

Avalon 总线规范_中文

altwra avalon specification

Avalon接口类型浅析

写一个verilog的avalon读写测试文件

avalon通信协议详细

FPGA 实现avalon 总线代码

avalon总线例程

avalon总线和AMBA总线有什么区别

avalon突发传输主设备代码

avalon总线突发传输的主设备代码

最新资源