写一个verilog的avalon读写测试文件

以下是一个简单的Verilog代码，用于测试Avalon总线的读写操作：

module Avalon_Test (
    input         clk,
    input         reset,
    input         read_req,
    input  [31:0] read_addr,
    output [31:0] read_data,
    input         write_req,
    input  [31:0] write_addr,
    input  [31:0] write_data,
    input         write_enable
);

// Avalon bus signals
reg   [31:0]   avalon_address;
wire  [31:0]   avalon_read_data;
reg   [31:0]   avalon_write_data;
reg           avalon_read_req;
reg           avalon_write_req;
reg           avalon_write_enable;

// Test variables
reg   [31:0]   test_data;
reg           test_write_enable;
reg           test_read_enable;
reg   [31:0]   test_address;

// Clock divider for slower data transfer
reg           clk_divider;

// Counter for data verification
reg   [31:0]   counter;

// Avalon slave module instantiation
Avalon_Slave dut (
    .clk                  (clk),
    .reset                (reset),
    .read_req             (avalon_read_req),
    .read_addr            (avalon_address),
    .read_data            (avalon_read_data),
    .write_req            (avalon_write_req),
    .write_addr           (avalon_address),
    .write_data           (avalon_write_data),
    .write_enable         (avalon_write_enable)
);

// Testbench
initial begin
    // Initialize variables
    test_data         = 0;
    test_write_enable = 0;
    test_read_enable  = 0;
    test_address      = 0;
    counter           = 0;
    clk_divider       = 0;

    // Reset the Avalon slave module
    reset = 1;
    #10;
    reset = 0;
    #10;

    // Write to the Avalon slave module
    test_data         = 123;
    test_write_enable = 1;
    test_address      = 4;
    #10;

    // Read from the Avalon slave module
    test_read_enable  = 1;
    test_address      = 4;
    #10;

    // Verify the read data
    if (test_data == avalon_read_data) begin
        $display("Data verification successful!");
    end else begin
        $display("Data verification failed!");
    end

    // End the simulation
    $finish;
end

// Clock divider
always @(posedge clk) begin
    if (clk_divider == 1000) begin
        clk_divider <= 0;
    end else begin
        clk_divider <= clk_divider + 1;
    end
end

// Write data to the Avalon slave module
always @(posedge clk) begin
    if (clk_divider == 0) begin
        avalon_address      <= test_address;
        avalon_write_data   <= test_data;
        avalon_write_req    <= test_write_enable;
        avalon_write_enable <= write_enable;
    end
end

// Read data from the Avalon slave module
always @(posedge clk) begin
    if (clk_divider == 0) begin
        avalon_address   <= test_address;
        avalon_read_req   <= test_read_enable;
    end
end

// Counter for data verification
always @(posedge clk) begin
    if (clk_divider == 0) begin
        counter <= counter + 1;
    end
end

// Assign the read data to the output
assign read_data = avalon_read_data;

endmodule

这个测试代码包括一个Avalon从设备（Avalon_Slave）模块和一个测试模块（Avalon_Test）。测试模块将从设备模块连接到Avalon总线，并通过写入和读取来测试总线操作。测试数据为123，写入地址为4，读取地址也为4。这个测试代码还包括一个计数器，用于验证读取的数据是否正确。