PND工具详解：2012年阿尔特拉公司用户指南

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PND工具说明文档详细介绍了Altera公司的一款专门针对设备特定的电源配送网络（Power Delivery Network, PDN）设计与优化的工具。该工具在2012年9月发布，适用于San Jose, CA的101 Innovation Drive办公地址，其网址为www.altera.com/UG-01064-1.1UserGuide。这份用户指南是专门为Altera产品的设计者和工程师编写的，旨在帮助他们理解和利用PND技术来优化芯片的电源管理，提高系统性能和能效。 PND工具的核心功能包括但不限于以下几点： 1. 设备定制：该工具针对Altera特定的芯片系列（如Arria, Cyclone, Hardcopy, MAX, MEGACORE, NIOS, Quartus, Stratix等）提供定制化的PDN设计支持，每个系列可能有不同的功率需求和特性，因此工具能够根据芯片的具体规格进行优化。 2. 功率路径分析：工具允许用户模拟和分析电路中的电源路径，以便识别可能的瓶颈、过载或电压降问题，并提出改进措施。 3. 电源完整性检查：通过考虑电源噪声和纹波，确保系统在不同工作模式下都能维持稳定的电源供应，这对于现代电子系统中的低功耗和高速运行至关重要。 4. 热管理：由于PDN对散热有直接影响，PND工具还能帮助设计师评估和优化热管理策略，以防止过热并延长设备寿命。 5. 电源效率：通过精细化的电源分配，该工具可以帮助工程师实现更高的能源利用率，符合绿色计算的趋势。 6. 更新和兼容性：用户指南强调获取最新版本的设备规格，因为随着技术发展，Altera可能会不断更新其产品和服务，以适应新的设计要求。 7. 法律声明：文档还包含了Altera公司的法律声明，确认了保修政策、责任限制以及第三方商标和版权的归属，确保用户在使用时遵守相关规定。 PND工具是Altera为硬件开发者提供的一个强大而专业的设计辅助工具，它简化了复杂的电源管理过程，提高了设计效率和产品质量，尤其是在高性能、低功耗的嵌入式和应用处理器领域。

1–2 Chapter 1: User Guide for the Device-Specific Power Delivery Network (PDN) Tool

PDN Decoupling Methodology Review

Device-Specific Power Delivery Network (PDN) Tool User Guide September 2012 Altera Corporation

PDN Circuit Topology

The PDN tool is based on a lumped equivalent model representation of the power

delivery network topology. Figure 1–1 shows a schematic representation of the circuit

topology, modeled as part of the tool. The PDN impedance profile is the

impedance-over-frequency looking from the device side.

For first order analysis, the voltage regulator module (VRM) can be simply modeled

as a series connected resistor and inductor, as shown in Figure 1–1. At low

frequencies, up to approximately 50 KHz, the VRM has a very low impedance and is

capable of responding to the instantaneous current requirements of the FPGA. The

equivalent series resistance (ESR) and equivalent series inductance (ESL) values can

be obtained from the VRM manufacturer. At higher frequency, the VRM impedance is

primarily inductive, making it incapable of meeting the transient current requirement.

PCB decoupling capacitors are used for reducing the PDN impedance up to tens of

MHz. The on-board discrete decoupling capacitors provides the required low

impedance depending on the capacitor intrinsic parasitics (R

, C

, L

) and the

capacitor mounting inductance (L

mntN

). The inter-planar capacitance between the

power-ground planes typically has lower inductance than the discrete decoupling

capacitor network, making it more effective at higher frequencies (tens of MHz). As

frequency increases (tens of MHz and above), the PCB decoupling capacitors become

less effective. The limitation comes from the parasitic inductance seen with respect to

the FPGA, which consists of capacitor mounting inductance, PCB spreading

inductance, ball grid array (BGA) via inductance, and packaging parasitic inductance.

All these parasitics are modeled in this PDN tool to capture the effect of the PCB

decoupling capacitors accurately. To simplify the circuit topology, all parasitics are

represented with lumped inductors and resistors despite the distributed nature of

PCB spreading inductance.

TARGET

According to Ohm’s law, voltage drop across a circuit is proportional to the current

flow through the circuit and impedance of the circuit. The transient component of

PDN current gives rise to voltage fluctuation within the PDN, which may lead to logic

and timing issues. You can reduce excessive voltage fluctuation by reducing PDN

impedance. One design guide line is target impedance Z

TARGET

Figure 1–1. PDN Topology

Chapter 1: User Guide for the Device-Specific Power Delivery Network (PDN) Tool 1–3

PDN Decoupling Methodology Review

September 2012 Altera Corporation Device-Specific Power Delivery Network (PDN) Tool User Guide

target

is defined using the maximum allowable voltage ripple and transient current

and is calculated as follows:

For example, to reliably decouple a 3.3-volt power rail that allows 5% of AC ripple

and a maximum 2 A current draw, 50% of which is transient current, the desired

target impedance is:

To accurately calculate the Z

target

for any power rail, the following information must

be known:

■ The maximum transient current requirements for all devices in the system that are

from manufacturers of the respective devices. You can calculate the maximum

transient current of a device using the maximum total current and the transient

current percentage.

1 The percentage of transient current is signal-pattern dependent. It changes

as the output signal pattern varies for drivers using the power rail. You

need to choose the value that represents the worst-case scenario of the

power rail. For information about recommended settings, refer to the table

in the Introduction tab of the PDN tool. Table 1–1 on page 1–4 is from the

PDN tool for a Stratix IV GX device. It lists the Stratix IV GX default power

supply voltage, the recommended settings of the transient current

percentage, and the allowable voltage ripple for power rails.

1 You can obtain accurate estimations on the maximum total current for

Altera devices using the Altera PowerPlay Early Power Estimator (EPE)

tool or the Quartus II PowerPlay Power Analyzer tools. You can download

the EPE tool for your target Altera device from the PowerPlay Early Power

Estimator (EPE) and Power Analyzer.

Equation 1–1.

Equation 1–2.

TARGET

VoltageRail

%Ripple

100

------------------- -







MaxTransientCurrent

----------------------------------------------------------

TARGET

3.30.05

2 x 0.5

--------------------------- -

0.165==

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