TI DLPC300入门教程：DLP显示控制器详解

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DLPC300是一款由TI公司推出的专为DLP3000 DMD（Digital Micromirror Device）设计的数字控制器，它旨在帮助初学者快速掌握抬头显示技术。这款控制器具有高度灵活性，具备多种特性，使得它在图像处理和显示应用中表现出色。首先，DLPC300的核心功能是通过其24位输入端口实现对DMD的精确控制，能够支持高达33.5MHz的像素时钟，这为高速、高质量的显示提供了可能。它支持三种不同的输入颜色深度： 1. **24位RGB8888**：这种模式提供最完整的颜色深度，每个像素由红、绿、蓝三个通道的8位数据组成，可以呈现丰富的色彩细节。 2. **4:4:4 YCrCb888**：这是一种常见的色彩空间，4:4:4表示每个颜色分量（亮度Y、红色C和蓝色Cb）都有相同的位深度，适合视频处理应用。 3. **18位RGB666** 或 **4:4:4 YCrCb666**：较低的位深度减少了存储和处理的要求，但仍能提供不错的图像质量，适用于对成本敏感的应用。 4. **16位R**：单色或低色彩深度模式，主要用于节省资源的简单应用。除了数据接口，DLPC300还包含时钟（CLK）、控制信号（Control）和专门的控制如BSA（Backlight System Addressing）、DADCtl（Digital-to-Analog Converter Control）等，这些用于同步和调整显示系统的各个方面。此外，它还提供了主处理器接口以及电源管理功能，包括VRESET（复位）、VBIAS（偏置电压）、VOFF（关断电压）和LED驱动器控制，以确保系统的稳定运行。为了方便用户操作，控制器配备了PWM（脉冲宽度调制）接口来调节LED亮度，并且支持I2C通信接口，便于扩展外部设备连接。此外，还有PCLK（像素时钟）和Mobile DDR RAM的地址和控制信号，用于数据传输和存储。在存储方面，DLPC300支持volatile（易失性）和non-volatile（非易失性）存储，包括连接到USB、以太网等外部设备的接口，确保数据的安全性和可靠性。在电源管理方面，它包括PARK模式和各种同步信号（HSYNC、VSYNC、PDM、DATAEN）的控制，有助于节能和优化显示性能。为了用户交互，控制器还提供了用户界面LED、传感器接口（LS_OUT、LS_Ctrl）以及照明光学设计，以适应不同应用场景。值得注意的是，产品文档中包含的重要注意事项强调了产品的可用性、保修政策、安全使用条件、知识产权声明以及生产数据的更新，用户在使用前应仔细阅读。 DLPC300是一款功能强大的DLP数字控制器，集成了丰富的接口、色彩处理选项和电源管理特性，是入门级和专业级抬头显示项目开发的理想选择。通过理解和掌握这款控制器，开发者能够构建出高性能、灵活且易于集成的显示解决方案。

DLPC300

www.ti.com.cn

ZHCS244C –JANUARY 2012–REVISED AUGUST 2015

Pin Functions (continued)

I/O

POWER

I/O

TYPE

CLK SYSTEM DESCRIPTION

NAME NO.

WHITE POINT CORRECTION LIGHT SENSOR I/F

CMP_OUT A6 VCC18 I

Async

Successive approximation ADC comparator output (DLPC300

input). Assumes a successive approximation ADC is

implemented with a light sensor and/or thermocouple feeding

one input of an external comparator and the other side of the

comparator driven from the DLPC300 CMP_PWM pin. If not

used, this signal should be pulled down to ground.

CMP_PWM B7 VCC18 O

Async

Successive approximation comparator pulse-duration

modulation input. Supplies a PWM signal to drive the

successive approximation ADC comparator used in light-to-

voltage light sensor applications. Should be left unconnected if

this function is not used.

CMP_PWR P5 VCC18 B

Async

Power control signal for the WPC light sensor and other analog

support circuits using the DLPC300 ADC. Alternatively, it

provides general-purpose I/O to the WPC microprocessor

internal to the DLPC300. Should be left unconnected if not

used.

TRIGGER CONTROL

OUTPUT_TRIGGER

N9 VCC18 B

Async

Trigger output. Indicates that a pattern or image is displayed on

the screen and is ready to be captured. With an optional FPGA,

this signal is connected to the FPGA trigger input. This signal is

configured as output and driven low when the DLPR300 serial

flash PROM is loaded by the DLPC300, but the signal is not

enabled. To enable this output, a write to I

C LED Enable and

Buffer Control register. If not used, this signal should be pulled

down to ground through an external resistor.

PATTERN CONTROL

PATTERN_INVERT

C7 VCC18 B

Async

Inverts the current 1-bit pattern held in the DLPC300 buffer.

When used with an optional FPGA, this signal should be

connected to DMC_TRC of the FPGA. This signal is configured

as output and driven low when the DLPR300 serial flash PROM

is loaded by the DLPC300, but the signal is not enabled. To

enable this output, a write to I

C LED Enable and Buffer

Control register. If not used, this signal should be pulled down

to ground through an external resistor.

OPTIONAL FPGA BUFFER MANAGEMENT INTERFACES

RD_BUF0

VCC18 B

Async

When not used with an optional FPGA, this signal should be

pulled down to ground through an external resistor. When used

with an optional FPGA, this signal should be connected to

RD_PTR_SDC[0] of the FPGA. RD_BUFF1 and RD_BUFF0

indicate to the FPGA one of the four buffers currently in use.

This signal is configured as output and driven low when the

DLPR300 serial flash PROM is loaded by the DLPC300, but

the signal is not enabled. To enable this output, a write to I

LED Enable and Buffer Control register.

RD_BUF1/I2C_ADDR_SEL

This signal is sampled when RESET is deasserted to choose

between two predefined 7-bit I

C slave addresses. If

I2C_ADDR_SEL signal is pulled-low, then the DLPC300's I

slave address is 1Bh. If I2C_ADDR_SEL signal is pulled-high,

then the DLPC300's I

C slave address is 1Dh. When used with

an optional FPGA, this signal should be connected to

RD_PTR_SDC[1] of the FPGA. RD_BUFF1 and RD_BUFF0

indicate to the FPGA one of the four buffers currently in use.

This signal is set to input upon deassertion of RESET and

configured as output and driven low when the DLPR300 serial

flash PROM is loaded by the DLPC300, but the signal is not

enabled. To enable this output, a write to I

C LED Enable and

Buffer Control register.

BUFFER_SWAP

When not used with an optional FPGA, this signal should be

pulled down to ground through an external resistor. When used

with an optional FPGA, this signal should be connected to

BUFF_SWAP_SEQ of the FPGA. BUFFER_SWAP indicates to

the FPGA when to advance the buffer. This signal is configured

as output and driven low when the DLPR300 serial flash PROM

is loaded by the DLPC300, but the signal is not enabled. To

enable this output, a write to I

C LED Enable and Buffer

Control register.

CONTROLLER MANUFACTURER TEST SUPPORT

DLPC300

www.ti.com.cn

ZHCS244C –JANUARY 2012–REVISED AUGUST 2015

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to VSS (ground).

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted).

(1)

MIN MAX UNIT

ELECTRICAL

Voltage applied to

(2)

VDD10 –0.5 1.32 V

VDD_PLL –0.5 1.32 V

VCC18 –0.5 2.75 V

VCC_FLSH –0.5 3.60 V

VCC_INTF –0.5 3.60 V

All other input terminals, V

–0.5 3.60 V

ENVIRONMENTAL

Junction temperature –30 105 ºC

stg

Storage temperature –40 125 ºC

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

(1)

±2000

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins

(2)

±500

(1) VCCIO represents the actual supply voltage applied to the corresponding I/O.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this

data sheet is achieved when operating the device by the Recommended Operating Conditions. No level of performance is

implied when operating the device above or below the recommended operating conditions limits.

MIN NOM MAX UNIT

ELECTRICAL

VDD10 Core logic supply voltage 0.95 1 1.05 V

VDD_PLL Analog PLL supply voltage 0.95 1 1.05 V

VCC18 I/O supply voltage (except flash and 24-bit RGB interface signals) 1.71 1.8 1.89 V

VCC_FLSH

Configuration and control I/O supply

voltage

1.8-V LVCMOS 1.71 1.8 1.89

V2.5-V LVCMOS 2.375 2.5 2.625

3.3-V LVCMOS 3.135 3.3 3.465

VCC_INTF 24-bit RGB interface supply voltage

1.8-V LVCMOS 1.71 1.8 1.89

V2.5-V LVCMOS 2.375 2.5 2.625

3.3-V LVCMOS 3.135 3.3 3.465

Input voltage, all other pins –0.3

VCCIO

(1)

+ 0.3

Output voltage, all other pins 0 VCCIO

(1)

ENVIRONMENTAL

Operating junction temperature –20 85 ºC

剩余51页未读，继续阅读

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