Allwinner F1C200s: ARM9处理器详解与功能特性

需积分: 36 144 浏览量更新于2024-07-17 收藏 10.76MB PDF 举报

Allwinner F1C200s用户手册是Allwinner公司针对移动应用处理器市场推出的一款最新产品。这款处理器基于ARM9架构，实现了高度的功能集成，特别强调在视频播放性能上的优势。F1C200s支持全高清视频解码，包括H.264、H.263、MPEG1/2/4等多种格式，确保了用户在娱乐体验上的高质量。音频方面，内置的音频编码器和I2S/PCM接口提供了出色的音质，使得连接相机等设备的TV-IN接口实现视频输入成为可能，同时通过TV-OUT接口与电视设备相连，支持视频输出。为了降低整体物料成本（BOM），F1C200s集成了DDR1内存，并配备了一系列通用外围设备，如USB OTG（On-The-Go）、UART（Universal Asynchronous Receiver/Transmitter）、SPI（Serial Peripheral Interface）、TWI（Two-Wire Interface）、TP（Touch Pad）、SD/MMC（Secure Digital/MultiMedia Card）以及CSI（Camera Serial Interface）等，这些特性使其在性能、低功耗和灵活性上超越竞争对手。值得注意的是，文档版权属于Allwinner Technology Co., Ltd.，所有复制或部分复制必须获得书面许可，并明确提及版权所有人。文档中的信息虽然被认为是准确可靠的，但Allwinner并不对使用结果承担任何责任，也不保证不会侵犯第三方专利或其他权利。此外，此文档并未授予任何形式的专利使用权，也没有明示或暗示任何类型的保修，包括适用于特定用途的适用性。实施解决方案或产品可能需要第三方许可，客户应自行处理相关事宜。 Allwinner F1C200s是一款集视频处理、音频解码、多种接口和经济性于一身的移动处理器，适合于对视频播放和多媒体功能有高要求的设备，如便携式视频播放器和智能电视盒等。在选择和使用时，开发者和制造商需要遵循文档中的声明和注意事项，以确保合法合规并充分利用其优势。

Revision History

4.2.5. Operation Mode ...................................................................................................................................... 146

4.2.5.1. Basic principle .............................................................................................................................. 146

4.2.5.2. Single-ended mode ...................................................................................................................... 146

4.2.5.3. Differential mode ......................................................................................................................... 147

4.2.5.4. Single touch detection ................................................................................................................. 147

4.2.5.5. Dual touch detection .................................................................................................................... 148

4.2.5.6. Touch pressure measurement ...................................................................................................... 148

4.2.5.7. Pen down detection, with programmable sensitivity .................................................................. 149

4.2.5.8. Median and averaging filter ......................................................................................................... 150

4.2.6. TP Register List ........................................................................................................................................ 151

4.2.7. TP Register Description ........................................................................................................................... 151

4.2.7.1. TP Control Register 0 .................................................................................................................... 151

4.2.7.2. TP Control Register 1 .................................................................................................................... 152

4.2.7.3. TP Control Register 2 .................................................................................................................... 153

4.2.7.4. TP Control Register 3

.................................................................................................................... 154

4.2.7.5. TP Interrupt FIFO Control Register ............................................................................................... 154

4.2.7.6. TP Interrupt FIFO Status Register ................................................................................................. 155

4.2.7.7. TP Common Data Register ............................................................................................................ 156

4.2.7.8. TP Data Register ........................................................................................................................... 156

4.3. Audio Codec ....................................................................................................................................................... 157

4.3.1. Overview ................................................................................................................................................. 157

4.3.2. Feature .................................................................................................................................................... 157

4.3.3. Block diagram .......................................................................................................................................... 157

4.3.4. Signal Description .................................................................................................................................... 157

Revision History

4.3.5. Power Description ................................................................................................................................... 158

4.3.6. Function Description ............................................................................................................................... 158

4.3.6.1. ADC ............................................................................................................................................... 158

4.3.6.2. Stereo ADC ................................................................................................................................... 158

4.3.6.3. Mixer ............................................................................................................................................ 158

4.3.6.4. Headphone Mixer ......................................................................................................................... 158

4.3.6.5. ADC Record Mixer ........................................................................................................................ 158

4.3.6.6. Analog Audio Input Path .............................................................................................................. 159

4.3.6.7. FM Input ....................................................................................................................................... 159

4.3.7. Audio Codec Register List ........................................................................................................................ 160

4.3.8. Audio Codec Register Description ........................................................................................................... 160

4.3.8.1. DAC Digital Part Control Register ................................................................................................. 160

4.3.8.2. DAC FIFO Control Register ............................................................................................................ 162

4.3.8.3. DAC FIFO Status Register .............................................................................................................. 164

4.3.8.4. DAC TX DATA Register ................................................................................................................... 164

4.3.8.5.

ADC FIFO Control Register ............................................................................................................ 165

4.3.8.6. ADC FIFO Status Register .............................................................................................................. 166

4.3.8.7. ADC RX DATA Register .................................................................................................................. 167

4.3.8.8. DAC Analog & Output MIXER Control Register ............................................................................ 167

4.3.8.9. ADC Analog and Input mixer Control Register ............................................................................. 169

4.3.8.10. ADC&DAC performance tuning Register .................................................................................... 170

4.3.8.11. Bias & DA16 Calibration Control Register 0 ................................................................................ 171

4.3.8.12. Bias & DA16 Calibration Control Register 1 ................................................................................ 172

4.3.8.13. DAC TX Counter Register ............................................................................................................ 172

Revision History

4.3.8.14. ADC RX Counter Register ............................................................................................................ 172

4.3.8.15. DAC Debug Register ................................................................................................................... 172

4.3.8.16. ADC Debug Register ................................................................................................................... 173

4.3.8.17. ADC DAP Control Register .......................................................................................................... 173

4.3.8.18. ADC DAP Left Control Register ................................................................................................... 174

4.3.8.19. ADC DAP Right Control Register ................................................................................................. 175

4.3.8.20. ADC DAP Parameter Register ..................................................................................................... 176

4.3.8.21. ADC DAP Left Average Coef Register .......................................................................................... 177

4.3.8.22. ADC DAP Left Decay & Attack Time Register .............................................................................. 177

4.3.8.23. ADC DAP Right Average Coef Register ........................................................................................ 177

4.3.8.24. ADC DAP Right Decay & Attack Time Register ........................................................................... 178

4.3.8.25. ADC DAP HPF Coef Register ........................................................................................................ 178

4.3.8.26. ADC DAP Left Input Signal Low Average Coef Register

.............................................................. 178

4.3.8.27. ADC DAP Right Input Signal Low Average Coef Register ............................................................ 178

4.3.8.28. ADC DAP Optimum Register ....................................................................................................... 179

Chapter 5. Display ............................................................................................................................................................. 180

5.1. TCON .................................................................................................................................................................. 181

5.1.1. Overview ................................................................................................................................................. 181

5.1.2. Feature .................................................................................................................................................... 181

5.1.3. Block Diagram ......................................................................................................................................... 181

5.1.3.1. LCD Timing Controller .................................................................................................................. 181

5.1.4. TCON Register List ................................................................................................................................... 182

5.1.5. TCON Register Description ...................................................................................................................... 183

5.1.5.1. TCON Control Register .................................................................................................................. 183

Revision History

5.1.5.2. TCON Interrupt Register 0 ............................................................................................................ 183

5.1.5.3. TCON Interrupt Register 1 ............................................................................................................ 184

5.1.5.4. TCON FRM Control Register ......................................................................................................... 184

5.1.5.5. TCON FRM Seed0 Red Register .................................................................................................... 184

5.1.5.6. TCON FRM Seed0 Green Register ................................................................................................. 184

5.1.5.7. TCON FRM Seed0 Blue Register ................................................................................................... 185

5.1.5.8. TCON FRM Seed1 Red Register .................................................................................................... 185

5.1.5.9. TCON FRM Seed1 Green Register ................................................................................................. 185

5.1.5.10. TCON FRM Seed1 Blue Register ................................................................................................. 185

5.1.5.11. TCON FRM Table Register 0 ........................................................................................................ 185

5.1.5.12. TCON FRM Table Register 1 ........................................................................................................ 185

5.1.5.13. TCON FRM Table Register 2 ........................................................................................................ 186

5.1.5.14. TCON FRM Table Register 3 ........................................................................................................ 186

5.1.5.15. TCON0 Control Register .............................................................................................................. 186

5.1.5.16. TCON Clock Control Register ...................................................................................................... 187

5.1.5.17. TCON0 Basic Timing Register 0 .................................................................................................. 187

5.1.5.18. TCON0 Basic Timing Register 1 .................................................................................................. 187

5.1.5.19. TCON0 Basic Timing Register 2 .................................................................................................. 188

5.1.5.20. TCON0 Basic Timing Register 3 .................................................................................................. 188

5.1.5.21. TCON0 HV Timing Register ......................................................................................................... 188

5.1.5.22. TCON0 CPU Interface Control Register ....................................................................................... 189

5.1.5.23. TCON0 CPU Write Register ......................................................................................................... 190

5.1.5.24. TCON0 CPU Read Register .......................................................................................................... 190

5.1.5.25. TCON0 CPU Read NX Register ....................................................................................................

190

Revision History

5.1.5.26. TCON0 IO Control Register 0 ...................................................................................................... 190

5.1.5.27. TCON0 IO Control Register 1 ...................................................................................................... 191

5.1.5.28. TCON1 Control Register .............................................................................................................. 191

5.1.5.29. TCON1 Basic Timing Register 0 .................................................................................................. 192

5.1.5.30. TCON1 Basic Timing Register 1 .................................................................................................. 192

5.1.5.31. TCON1 Basic Timing Register 2 .................................................................................................. 192

5.1.5.32. TCON1 Basic Timing Register 3 .................................................................................................. 193

5.1.5.33. TCON1 Basic Timing Register 4 .................................................................................................. 193

5.1.5.34. TCON1 Basic Timing Register 5 .................................................................................................. 193

5.1.5.35. TCON1 IO Control Register 0 ...................................................................................................... 193

5.1.5.36. TCON1 IO Control Register 1 ...................................................................................................... 194

5.1.5.37. TCON Debug Information Register ............................................................................................. 194

5.2. Display Engine Front-End ................................................................................................................................... 196

5.2.1. Overview ................................................................................................................................................. 196

5.2.2. Feature .................................................................................................................................................... 196

5.2.3. Block Diagram ......................................................................................................................................... 196

5.2.4. DEFE Register List .................................................................................................................................... 196

5.2.5. DEFE Register Description ....................................................................................................................... 198

5.2.5.1. DEFE Module Enable Register ...................................................................................................... 198

5.2.5.2. DEFE Frame Process Control Register .......................................................................................... 198

5.2.5.3. DEFE CSC Bypass Register ............................................................................................................. 199

5.2.5.4. DEFE Algorithm Selection Register ............................................................................................... 200

5.2.5.5. DEFE Line Interrupt Conrtol Register............................................................................................ 200

5.2.5.6. DEFE Input Channel 0 Buffer Address Register ............................................................................ 200

剩余351页未读，继续阅读

prestofat

粉丝: 3
资源: 5

Allwinner F1C200s: ARM9处理器详解与功能特性

f1c200s_datasheet.pdf

MELIS 用户编程手册-Orange 编程指南.pdf

Allwinner_F1C200s_Datasheet_V1.1.pdf

Allwinner_F1C200s_User_Manual_V1.2.pdf

allwinner_f1c200s_user_manual_v1_2_全志f1c200s编程手册_

Allwinner_F1C200s_User_Manual_V1.0

allwinner-f1c200s-user-manual-v1-2.pdf 绝对完整版

全志Allwinner的f1c100s和a20手册User_Manual

F1C200S.rar

Allwinner F1C200s用户手册v1.2：完整版技术指南

最新资源