时序分析入门指南：TimeQuest用户精华教程

3星 · 超过75%的资源需积分: 9 53 浏览量更新于2024-07-19 收藏 4.11MB PDF 举报

"时序分析用户手册" 《时序分析用户手册》是一本针对时序分析初学者的专业指南，由Ryan Scoville编写，旨在整合作者在时序分析领域的经验，提供一个综合性的学习资源。该手册虽仍处于不断更新和完善中，但已包含了大部分时序分析的基础知识，对大多数用户来说已经足够使用。时序分析是数字系统设计中的关键部分，主要用于评估电路在实际工作条件下的性能，确保信号能在规定的时间内正确传输，避免出现数据丢失或错误。TimeQuest是Altera公司提供的一款强大的时序分析工具，能够帮助设计师优化设计以满足速度性能要求。手册的结构清晰，推荐使用书签功能进行导航，以快速定位关键点。作者强调，虽然页面内容丰富，但通过书签和超链接可以轻松地在不同概念之间跳转。尤其是“Getting Started”部分，这是初学者的入门指南，包含了解析时序分析的基础知识和TimeQuest的基本操作，对于理解后续的实例和高级概念至关重要。在手册中，读者可以期待找到以下主题的详细讲解： 1. **时序约束**：如何定义和应用时序约束，以指导TimeQuest进行分析，确保设计满足速度要求。 2. **路径分析**：学习如何识别和分析关键路径，这些路径决定了设计的最慢时钟周期。 3. **时序报告**：理解TimeQuest生成的各种时序报告，如详尽的时序总结、路径详细信息等，以及如何解读这些报告来优化设计。 4. **时钟树综合**：了解时钟树的构建过程及其对时序性能的影响。 5. **时序优化技术**：包括逻辑优化、布线调整、时钟树调整等，以提升设计速度。 6. **错误修复策略**：当遇到时序违规（Timing Violation）时，如何进行有效的故障排查和修复。 7. **高级特性**：深入探讨TimeQuest的高级功能，如动态时序分析、功耗管理等。这本手册不仅适合初学者，也对有经验的设计师有价值，因为它提供了一种系统性的学习和参考方法，减少了在论坛上寻找答案的时间。定期更新的承诺意味着手册将随着Altera TimeQuest软件的更新而保持最新，确保读者能够获取到最新的知识和技术。

As can be seen, we just described a circuit outside the FPGA. We also now have a

FPGA.

Step 3) Determine the default setup and hold relationship between the

FPGA clock and virtual clock

This step requires the user to determine the setup and hold relationship between the clock

inside the FPGA and the virtual external clock. This is usually very straightforward, as in most

cases the launch clock and latch clock have the same period and are edge aligned, and hence

have a setup relationship equal to the clock period, and a hold relationship of 0ns, as shown in

the top-left example:

For I/O, the virtual clock will be the launch clock for input constraints, and the latch

clock for output constraints. I've shown a few more cases, but won't delve into too much detail

on how to determine the setup and hold relationship, which is covered in-depth in Timing

Analysis Basics.

Rather than delve into calculating the relationship, I'll show how TimeQuest will show

the relationship it is using, and hence the user doesn't have to figure it out beforehand. For

example, a user might have a 100MHz clock coming into the FPGA, which goes through a PLL

and drives data out at 100Mbps. After following the previous steps, the user creates a 10ns

external clock and applies it to the output ports like so:

create_clock -period 10.0 -name tx_clk_ext

set_output_delay -clock tx_clk_ext -max 0.0 [get_ports {TX_DATA[*] TX_PAR}]

set_output_delay -clock tx_clk_ext -min 0.0 [get_ports TX_DATA[*] TX_PAR}]

In this example, they've created a virtual clock called tx_clk_ext. They also said the ports

TX_DATA[*] and TX_PAR drive external registers clocked by tx_clk_ext, and the max and min

delay to those registers is 0.0ns. Since the internal clock also has a period of 10.0ns, and neither

is phase-shifted, then the default setup relationship is 10.0ns and the default hold relationship is

0.0ns. If the user is unsure of this, they can read in the .sdc file using the iterative method and

run report_timing to those ports. In TimeQuest's pull-down menu: Reports -> Custom Reports -

> Report Timing. Simply put the virtual clock name, tx_clk_ext, in the To Clock section, and run

report_timing twice, once for setup and once for hold. In this example, I got the following two

reports:

The left panel is the setup analysis, and the Relationship column, shown in red, is 10ns.

This is expected, as we have a 10ns clock feeding another 10ns clock. Below the Summary of

Paths is the detail for the first path. The 10ns is used such that the launch edge time is 0ns and

the latch edge time is 10ns. Likewise for hold analysis, the relationship is 0ns. The launch edge

time is 0ns and the latch edge time is 0ns.

So what is this really saying? When the launch clock comes into the FPGA, travels to the

source register, which is the output register in this case, then through the output port to the

external register, it must get there in greater than 0ns(the hold relationship) and less than

10ns(the setup relationship). Since our external -max and -min delays are 0ns, i.e. there is no

external delay, than the delay within the FPGA must be greater than 0ns and less than 10ns. At

this point, we have a full constraint that TimeQuest can analyze, but it is probably not the

analysis we want.

Step 4) Add multicycles

This step is usually unnecessary. But if step 3) resulted in a default analysis that is

incorrect, the user may want to modify the setup and hold relationships with multicycles. The

most common cases for this are when the user wants to open the window or shift the window.

Note that we are not accounting for external delays like the Tsu or Tco of an external device or

board delays, as that will be done in step 5. This step is just to make sure the clock relationships

are correct.

An example would be interfacing to a flash device that takes multiple clock cycles to

perform each operation, than the user may want to open the window. An example may look like

so:

set_multicycle_path -setup -to [get_ports {FLASH_DATA[*]}] 4

set_multicycle_path -hold -to [get_ports {FLASH_DATA[*]}] 3

These two assignments tell TimeQuest that there are 4 clock cycles for the

FLASH_DATA to get out of the FPGA. So if the original setup and hold relationships were

10ns and 0ns, they would now be 40ns and 0ns(assuming the clock period is 10ns).

If the clock inside the FPGA has a phase-shift, generally through a PLL, and the external

clock does not, then the user may want to shift the window. For example, if the FPGA clock

feeding an output register were phase-shifted -500ps in order to help meet output timing, the

default setup relationship would be 500ps. To shift the window, the user would add:

set_multicycle_path -setup -to [get_ports {FLASH_DATA[*]}] 2

or:

set_multicycle_path -setup -from [get_clocks {pll|clk[0]} -to [get_clocks clk_ext] 2

The first one modifies the clock relationship on the output path, while the second one

modifies all relationships between these clocks. Either one of these will work as long as they

cover what the user wants covered. If the clocks have a 10ns period, the multicycle will modify

the setup relationship from 0.5ns to 9.5ns, and the hold relationship from -9.5ns to 0.5ns.

Note that if the FPGA clock were phase-shifted forward a little, then a multicycle would

most likely not be necessary. If the default setup relationship were 10ns, and the source clock

inside the FPGA were phase-shifted 500ps forward, then the default relationship would become

9.5ns, which is probably what the user wants.

Inputs work the opposite, whereby if the user phase-shifts the latching clock inside the

FPGA forward a little, then they probably want a multicycle to shift the window, but if they

phase-shift the clock back, they probably do not. This is easily seen by drawing the launch and

latch clock waveforms, as explained in the section on default setup and hold, specifically the

affect of phase-shifts.

Step 5) Modify the -max and -min delays to account for external delays.

Now that we have the correct setup and hold relationship, it is time to modify the -max

and -min values. They are currently set to 0, which means there is no external delay to the

data window is used by the external device and board delays, only leaving part of the data

window for the FPGA. The -max and -min values account for these external delays. Let's see

how they affect the analysis before determining how they account for external delays.

With both -max and -min at 0, we are stating that there are no external delays, and

basically have no affect on the analysis. As the -max value gets larger, it cuts into our setup

relationship. So if the our default setup relationship were 10ns, and the -max output delay were

4ns, that would mean the FPGA must get it's data out in less than 6ns to meet timing. Note the

setup relationship is still 10ns, but the FPGA's delay plus the external delay must be less than

that. So the larger -max gets, the more quickly the FPGA needs to get its data out and the harder

it is to meet timing. As the -max value gets larger, the FPGA needs a faster Tco.

The -min value is often more confusing because it works in the opposite way, whereby

the smaller it gets, the harder it is to meet timing. If the hold relationship is 0ns, and the -min

value was -1ns, then the only way to meet timing would be for the FPGA to get its data out in

more than 1ns. Looking at this through waveforms:

The top waveform shows the default relationships, while the second waveform shows

what happens after accounting for the external delays. Rather than the FPGA needing to get it's

data out between 0ns and 10ns, it must now get out between 1ns and 6ns. Likewise, for internal

paths, if a user entered similar external delays:

剩余132页未读，继续阅读

zcl_33

粉丝: 16
资源: 61

时序分析入门指南：TimeQuest用户精华教程

静态时序分析基本原理和时序分析模型

Altera最新Timequest时序分析高级培训教材

6011系列时序/噪声分析仪用户手册

Xilinx时序分析手册：Timing Analyzer深度指南

PrimeTime与PrimeTimeSI用户手册H-2012.12版：时序分析工具详解

Synopsys PrimeTime ug.pdf：2006.12版静态时序分析手册指南

DDR2数据手册：时序分析与IP设置指南

时序分析资料

静态时序分析简明教程

Xilinx FPGA的时序分析指南

最新资源