6
TCA9545A
ZHCSC52D –JANUARY 2014–REVISED NOVEMBER 2019
www.ti.com.cn
Copyright © 2014–2019, Texas Instruments Incorporated
Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
(4) C
io(ON)
depends on the device capacitance and load that is downstream from the device.
C
i
A1, A0
V
I
= V
CC
or GND
(2)
1.65 V to 5.5 V
4.5 6
pFINT3–INT0 4.5 6
RESET 4.5 5.5
C
io(OFF)
(4)
SCL, SDA
V
I
= V
CC
or
GND
(2)
Switch OFF 1.65 V to 5.5 V
15 19
pF
SC3–SC0, SD3–SD0 6 8
R
ON
Switch on-state resistance
V
O
= 0.4 V I
O
= 15 mA
4.5 V to 5.5 V 4 10 16
Ω
3 V to 3.6 V 5 13 20
V
O
= 0.4 V I
O
= 10 mA
2.3 V to 2.7 V 7 16 45
1.65 V to 1.95 V 10 25 70
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the V
IH
min of the SCL signal), in order
to bridge the undefined region of the falling edge of SCL.
(2) C
b
= total bus capacitance of one bus line in pF
(3) Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 5)
6.6 I
2
C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
STANDARD MODE
I
2
C BUS
FAST MODE
I
2
C BUS
UNIT
MIN MAX MIN MAX
f
scl
I
2
C clock frequency 100 400 kHz
t
sch
I
2
C clock high time 4 0.6 μs
t
scl
I
2
C clock low time 4.7 1.3 μs
t
sp
I
2
C spike time 50 50 ns
t
sds
I
2
C serial-data setup time 250 100 ns
t
sdh
I
2
C serial-data hold time 0
(1)
0
(1)
μs
t
icr
I
2
C input rise time 1000 20 + 0.1C
b
(2)
300 ns
t
icf
I
2
C input fall time 300 20 + 0.1C
b
(2)
300 ns
t
ocf
I
2
C output fall time 10-pF to 400-pF bus 300 20 + 0.1C
b
(2)
300 ns
t
buf
I
2
C bus free time between stop and start 4.7 1.3 μs
t
sts
I
2
C start or repeated start condition setup 4.7 0.6 μs
t
sth
I
2
C start or repeated start condition hold 4 0.6 μs
t
sps
I
2
C stop condition setup 4 0.6 μs
t
vdL(Data)
Valid-data time (high to low)
(3)
SCL low to SDA output low
valid
1 1 μs
t
vdH(Data)
Valid-data time (low to high)
(3)
SCL low to SDA output high
valid
0.6 0.6 μs
t
vd(ack)
Valid-data time of ACK condition
ACK signal from SCL low
to SDA output low
1 1 μs
C
b
I
2
C bus capacitive load 400 400 pF
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