TLC2543系列12位模拟到数字转换器详解与规格介绍
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更新于2024-07-31
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TLC2543是一款由ALCON公司的12位分辨率的模拟到数字转换器（A/D Converter），特别适合于需要快速数据传输的应用场景。该芯片系列包括TLC2543C、TLC2543I和TLC2543M，均采用先进的CMOS技术制造，具有高性能和低功耗的特点。
这些器件的核心功能是将模拟信号转换为数字信号，每个转换器有11个模拟输入通道，支持单极性或双极性输出操作，根据所施加的电压参考，数字输出可以是带符号的二进制表示，其中最高位或最低位可以根据编程进行选择。这意味着用户可以根据需求灵活定制输出格式。
TLC2543的主要特性包括：
1. 12位分辨率：提供了非常高的精度，能有效捕捉输入信号的微小变化，这对于需要高精度测量或信号处理的应用至关重要。
2. 快速转换时间：10微秒的转换周期，这意味着在正常工作温度下，数据采集的速度非常快，能够满足实时或高速数据传输的需求。
3. 内置自测模式：有三种内置的自我测试模式，确保了设备的稳定性和可靠性。
4. 内建采样保持功能：防止信号在转换过程中因外部干扰而失真，提高了转换结果的准确性。
5. 线性误差：最大不超过1LSB（Least Significant Bit，最低有效位）的误差，保证了转换的精确度。
6. 集成系统时钟：芯片内部集成时钟，简化了系统设计，降低了对外部时钟源的依赖。
7. 串行控制：通过三个控制输入（芯片选择、输入/输出时钟和地址输入）与主机处理器或外围设备进行串行通信，便于接口设计。
8. 电源管理：具有可编程的休眠模式，可以在不使用时节省电能。
9. 可编程输出数据长度：用户可以根据实际应用调整输出数据的长度，增加了灵活性。
10. 应用报告：ALCON公司还提供了详细的使用手册和应用报告，为开发者提供了宝贵的参考和指导。
TLC2543广泛应用于工业自动化、仪表测量、音频处理、数据采集等领域，特别是对于需要快速、高精度模拟信号数字化转换的系统设计，TLC2543是理想的选择。在使用时，应仔细阅读规格书并按照指南进行操作，以充分利用其全部优势。
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range,
V
CC
= V
ref+
= 4.5 V to 5.5 V, f
(I/O
CLOCK)
= 4.1 MHz
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
E
L
Linearity error (see Note 5) See Figure 2 ±1 LSB
E
D
Differential linearity error See Figure 2 ±1 LSB
E
O
Offset error (see Note 6)
See Note 2 and
Figure 2
±1.5 LSB
E
G
Gain error (see Note 6)
See Note 2 and
Figure 2
±1 LSB
E
T
Total unadjusted error (see Note 7) ±1.75 LSB
DATA INPUT = 1011 2048
Self-test output code (see Table 3 and Note 8)
DATA INPUT = 1100
0
DATA INPUT = 1101 4095
t
(conv)
Conversion time See Figures 9–14 8 10 µs
t
c
Total cycle time (access, sample, and conversion)
See Figures 9–14
and Note 9
10 + total
I/O CLOCK
periods +
t
d(I/O-EOC)
µs
t
acq
Channel acquisition time (sample)
See Figures 9–14
and Note 9
4 12
I/O
CLOCK
periods
t
v
Valid time, DATA OUT remains valid after I/O CLOCK↓ See Figure 6 10 ns
t
d(I/O-DATA)
Delay time, I/O CLOCK↓ to DATA OUT valid See Figure 6 150 ns
t
d(I/O-EOC)
Delay time, last I/O CLOCK↓ to EOC↓ See Figure 7 1.5 2.2 µs
t
d(EOC-DATA)
Delay time, EOC↑ to DATA OUT (MSB/LSB) See Figure 8 100 ns
t
PZH
, t
PZL
Enable time, CS↓ to DATA OUT (MSB/LSB driven) See Figure 3 0.7 1.3 µs
t
PHZ
, t
PLZ
Disable time, CS↑ to DATA OUT (high impedance) See Figure 3 70 150 ns
t
r(EOC)
Rise time, EOC See Figure 8 15 50 ns
t
f(EOC)
Fall time, EOC See Figure 7 15 50 ns
t
r(bus)
Rise time, data bus See Figure 6 15 50 ns
t
f(bus)
Fall time, data bus See Figure 6 15 50 ns
t
d(I/O-CS)
Delay time, last I/O CLOCK↓ to CS↓ to abort conversion
(see Note 10)
5 µs
†
All typical values are at T
A
= 25°C.
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that
applied to REF– convert as all zeros (000000000000).
5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
6. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified
gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the
nominal midstep value at the offset point.
7. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic.
9. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 7).
10. Any transitions of CS
are recognized as valid only when the level is maintained for a setup time. CS must be taken low at ≤ 5 µs
of the tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5 µs and 10 µs, the result is uncertain as to whether
the conversion is aborted or the conversion results are valid.
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