dsPIC33CK256MP508 家族数据手册：高性能数字信号控制器

需积分: 10 25 浏览量更新于2024-07-14 收藏 3.94MB PDF 举报

"DSPIC33CK64MP505-IPT-other-datasheet.pdf" 本文将详细讨论Microchip Technology Inc.的dsPIC33CK系列微控制器，特别是DS70005349C-page1提及的dsPIC33CK256MP508型号。该微控制器以其高性能、低功耗特性和丰富的内置功能集成为嵌入式系统设计提供了强大支持。 dsPIC33CK256MP508是一款基于16位dsPIC33CK CPU的微控制器，具有3.0V至3.6V的工作电压范围，可在-40°C到+125°C的温度条件下稳定工作，且能支持高达100MIPS的运算速度。它配备有32KB至256KB的带有错误校验（ECC）功能的程序闪存和8KB至24KB的RAM，以存储程序代码和数据。在处理器性能方面，这款微控制器具备快速6周期除法器，支持实时更新功能，以及高效（C语言和汇编语言）架构。它拥有40位宽的累加器，单周期乘法/除法（MAC/MPY）能力，并具备双数据取指功能，能实现混合符号乘法及硬件除法。此外，它还支持32位乘法操作，并提供四组中断上下文保存寄存器，包括累加器和STATUS寄存器，以便快速处理中断事件。零开销循环特性则提高了循环密集型代码的执行效率。时钟管理是该微控制器的另一大亮点。它配备了内部振荡器，可编程锁相环（PLL）和振荡器时钟源，能够输出参考时钟，并包含失败安全时钟监视器（FSCM）。快速唤醒和启动功能确保了高效能的电源管理，同时还有一个备用的内部振荡器。在电源管理上，dsPIC33CK256MP508提供了多种低功耗模式，如睡眠、空闲和打盹模式。此外，它内置了上电复位和欠压复位功能，确保系统在各种电源条件下稳定运行。对于高速脉宽调制（PWM）应用，该微控制器具有8对PWM通道，最高可达250ps的PWM分辨率，支持上升沿和下降沿的死区时间，以及死区时间补偿。针对高频操作，它还具备时钟切分功能，进一步增强了PWM性能。 dsPIC33CK256MP508是一款高度集成的微控制器，适用于需要高性能计算、低功耗和高级定时功能的嵌入式应用，如电机控制、电源转换、工业自动化以及其他实时控制任务。其丰富的外设和强大的处理能力使其成为许多复杂系统设计的理想选择。

dsPIC33CK256MP508 FAMILY

DS70005349C-page 16  2017-2018 Microchip Technology Inc.

Referenced Sources

This device data sheet is based on the following

individual chapters of the “dsPIC33/PIC24 Family

Reference Manual”. These documents should be

considered as the general reference for the operation

of a particular module or device feature.

• “Introduction” (DS70573)

• “dsPIC33E Enhanced CPU” (DS70005158)

• “dsPIC33E/PIC24E Program Memory” (DS70000613)

• “Data Memory” (DS70595)

• “Dual Partition Flash Program Memory” (DS70005156)

• “Flash Programming” (DS70609)

• “Reset” (DS70602)

• “Interrupts” (DS70000600)

• “I/O Ports with Edge Detect” (DS70005322)

• “Oscillator Module with High-Speed PLL” (DS70005255)

• “Direct Memory Access Controller (DMA)” (DS39742)

• “CAN Flexible Data-Rate (FD) Protocol Module” (DS70005340)

• “High-Resolution PWM with Fine Edge Placement” (DS70005320)

• “12-Bit High-Speed, Multiple SARs A/D Converter (ADC)” (DS70005213)

• “High-Speed Analog Comparator Module” (DS70005280)

• “Quadrature Encoder Interface (QEI)” (DS70000601)

• “Multiprotocol Universal Asynchronous Receiver Transmitter (UART) Module” (DS70005288)

• “Serial Peripheral Interface (SPI) with Audio Codec Support” (DS70005136)

• “Inter-Integrated Circuit (I

C)” (DS70000195)

• “Parallel Master Port (PMP)” (DS70005344)

• “Single-Edge Nibble Transmission (SENT) Module” (DS70005145)

• “Timer1 Module” (DS70005279)

• “Capture/Compare/PWM/Timer (MCCP and SCCP)” (DS33035)

• “Configurable Logic Cell (CLC)” (DS70005298)

• “Peripheral Trigger Generator (PTG)” (DS70000669)

• “32-Bit Programmable Cyclic Redundancy Check (CRC)” (DS30009729)

• “Current Bias Generator (CBG)” (DS70005253)

• “Deadman Timer” (DS70005155)

• “Watchdog Timer and Power-Saving Modes” (DS70615)

• “CodeGuard™ Security” (DS70634)

• “Dual Watchdog Timer” (DS70005250)

• “Programming and Diagnostics” (DS70608)

Note 1: To access the documents listed below,

browse to the documentation section of the

dsPIC33CK256MP508 product page of the

Microchip website (www.microchip.com) or

select a family reference manual section

from the following list.

In addition to parameters, features and

other documentation, the resulting page

provides links to the related family

reference manual sections.

dsPIC33CK256MP508 FAMILY

DS70005349C-page 18  2017-2018 Microchip Technology Inc.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

(1)

Type

Buffer

Type

PPS Description

AN0-AN23

ANA0-ANA1

ANN0-ANN2

Analog

Analog input channels

Analog alternate inputs

Analog negative inputs

ADTRG I ST Yes ADC Trigger Input 31

CLKI

CLKO

ST/

CMOS

—

External Clock (EC) source input. Always associated with OSCI pin

function.

Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillator mode. Optionally functions as CLKO in RC and EC

modes. Always associated with OSCO pin function.

OSCI

OSCO

I/O

ST/

CMOS

—

Oscillator crystal input. ST buffer when configured in RC mode;

CMOS otherwise.

Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillator mode. Optionally functions as CLKO in RC and EC

modes.

REFCLKO

REFOI

—

Yes

Reference clock output

Reference clock input

INT0

INT1

INT2

INT3

Yes

External Interrupt 0

External Interrupt 1

External Interrupt 2

External Interrupt 3

IOCA<4:0>

IOCB<15:0>

IOCC<15:0>

IOCD<15:0>

IOCE<15:0>

Interrupt-on-Change input for PORTA

Interrupt-on-Change input for PORTB

Interrupt-on-Change input for PORTC

Interrupt-on-Change input for PORTD

Interrupt-on-Change input for PORTE

RP32-RP71 I/O ST Yes Remappable I/O ports

RA0-RA4 I/O ST No PORTA is a bidirectional I/O port

RB0-RB15 I/O ST No PORTB is a bidirectional I/O port

RC0-RC15 I/O ST No PORTC is a bidirectional I/O port

RD0-RD15 I/O ST No PORTD is a bidirectional I/O port

RE0-RE15 I/O ST No PORTE is a bidirectional I/O port

T1CK I ST Yes Timer1 external clock input

CAN1RX

CAN1

—

Yes

CAN1 receive input

CAN1 transmit output

U1CTS

U1RTS

U1RX

U1TX

U1DSR

U1DTR

—

Yes

UART1 Clear-to-Send

UART1 Request-to-Send

UART1 receive

UART1 transmit

UART1 Data-Set-Ready

UART1 Data-Terminal-Ready

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

PPS = Peripheral Pin Select TTL = TTL input buffer DIG = Digital

Note 1: Not all pins are available in all package variants. See the “Pin Diagrams” section for pin availability.

2: PWM4L and PWM4H pins are available on PPS as well as dedicated.

3: SPI2 supports dedicated pins as well as PPS on 48, 64 and 80-pin devices.

4: Only 48, 64 and 80-pin devices have all eight PWM output pairs on dedicated pins. Refer to the “Pin

Diagrams” for PWM pin availability on other packages.

 2017-2018 Microchip Technology Inc. DS70005349C-page 19

dsPIC33CK256MP508 FAMILY

U2CTS

U2RTS

U2RX

U2TX

U2DSR

U2DTR

—

Yes

UART2 Clear-to-Send

UART2 Request-to-Send

UART2 receive

UART2 transmit

UART2 Data-Set-Ready

UART2 Data-Terminal-Ready

U3CTS

U3RTS

U3RX

U3TX

U3DSR

U3DTR

—

Yes

UART3 Clear-to-Send

UART3 Request-to-Send

UART3 receive

UART3 transmit

UART3 Data-Set-Ready

UART3 Data-Terminal-Ready

SCK1

SDI1

SDO1

SS1

I/O

—

Yes

Synchronous serial clock input/output for SPI1

SPI1 data in

SPI1 data out

SPI1 slave synchronization or frame pulse I/O

SCK2

SDI2

SDO2

SS2

I/O

—

Yes

(3)

Yes

(3)

Yes

(3)

Yes

(3)

Synchronous serial clock input/output for SPI2

SPI2 data in

SPI2 data out

SPI2 slave synchronization or frame pulse I/O

SCK3

SDI3

SDO3

I/O

—

Yes

Synchronous serial clock input/output for SPI3

SPI3 data in

SPI3 data out

SPI3 slave synchronization or frame pulse I/O

SCL1

SDA1

ASCL1

ASDA1

I/O

Synchronous serial clock input/output for I2C1

Synchronous serial data input/output for I2C1

Alternate synchronous serial clock input/output for I2C1

Alternate synchronous serial data input/output for I2C1

SCL2

SDA2

ASCL2

ASDA2

I/O

Synchronous serial clock input/output for I2C2

Synchronous serial data input/output for I2C2

Alternate synchronous serial clock input/output for I2C2

Alternate synchronous serial data input/output for I2C2

SCL3

SDA3

ASCL3

ASDA3

I/O

Synchronous serial clock input/output for I2C3

Synchronous serial data input/output for I2C3

Alternate synchronous serial clock input/output for I2C3

Alternate synchronous serial data input/output for I2C3

QEIA1-QEIA2

QEIB1-QEIB2

QEINDX1-QEINDX2

QEIHOM1-QEIHOM2

QEICMP1-QEICMP2

—

Yes

QEI Inputs A1 and A2

QEI Inputs B1 and B2

QEI Index Inputs 1 and 2

QEI Home Inputs 1 and 2

QEI Comparator Outputs 1 and 2

SENT1-SENT2

SENT1OUT-SENT2OUT

—

Yes

SENT1 and SENT2 inputs

SENT1 and SENT2 outputs

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

(1)

Type

Buffer

Type

PPS Description

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

PPS = Peripheral Pin Select TTL = TTL input buffer DIG = Digital

Note 1: Not all pins are available in all package variants. See the “Pin Diagrams” section for pin availability.

2: PWM4L and PWM4H pins are available on PPS as well as dedicated.

3: SPI2 supports dedicated pins as well as PPS on 48, 64 and 80-pin devices.

4: Only 48, 64 and 80-pin devices have all eight PWM output pairs on dedicated pins. Refer to the “Pin

Diagrams” for PWM pin availability on other packages.

dsPIC33CK256MP508 FAMILY

DS70005349C-page 20  2017-2018 Microchip Technology Inc.

TMS

TCK

TDI

TDO

—

JTAG Test mode select pin

JTAG test clock input pin

JTAG test data input pin

JTAG test data output pin

PCI8-PCI18

PCI19-PCI22

PWM1L-PWM8L

(2)

PWM1H-PWM8H

(2)

PWMEA-PWMED

—

Yes

(4)

Yes

PWM PCI Inputs 8 through 18

PWM PCI Inputs 19 through 22

PWM Low Outputs 1 through 8

PWM High Outputs 1 through 8

PWM Event Outputs A through D

CMP1A-CMP3A

CMP1B-CMP3B

CMP1C-CMP3C

CMP1D-CMP3D

Analog

Comparator Channels 1A through 3A inputs

Comparator Channels 1B through 3B inputs

Comparator Channels 1C through 3C inputs

Comparator Channels 1D through 3D inputs

DACOUT1 O — No DAC output voltage

TCKI1-TCKI9

ICM1-ICM9

OCFA-OCFD

OCM1-OCM9

—

Yes

SCCP/MCCP Timer Inputs 1 through 9

SCCP/MCCP Capture Inputs 1 through 9

SCCP/MCCP Fault Inputs A through D

SCCP/MCCP Compare Outputs 1 through 9

IBIAS0-IBIAS3

ISRC0-ISRC3

Analog

50 µA Constant-Current Outputs 0 through 3

10 µA Constant-Current Outputs 0 through 3

OA1IN+

OA1IN-

OA1OUT

OA2IN+

OA2IN-

OA2OUT

OA3IN+

OA3IN-

OA3OUT

—

Op Amp 1+ Input

Op Amp 1- Input

Op Amp 1 Output

Op Amp 2+ Input

Op Amp 2- Input

Op Amp 2 Output

Op Amp 3+ Input

Op Amp 3- Input

Op Amp 3 Output

PMA0/PMALL

PMA1/PMALH

PMA14/PMCS1

PMA15/PMCS2

PMA2-PMA13

PMD0-PMD15

PMRD/PMWR

PMWR/PMENB

PSA0

PSA1

PSCS

PSRD

PSWR

I/O

ST/TTL

PMP Address 0 or address latch low

PMP Address 1 or address latch high

PMP Address 14 or Chip Select 1

PMP Address 15 or Chip Select 2

PMP Address Lines 2-13

PMP Data Lines 0-15

PMP read or read/write signal

PMP write or data enable signal

PMP Slave Address 0

PMP Slave Address 1

PMP slave chip select

PMP slave write

PMP slave read

CLCINA-CLCIND

CLC1OUT-CLC4OUT

—

Yes

CLC Inputs A through D

CLC Outputs 1 through 4

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

(1)

Type

Buffer

Type

PPS Description

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

PPS = Peripheral Pin Select TTL = TTL input buffer DIG = Digital

Note 1: Not all pins are available in all package variants. See the “Pin Diagrams” section for pin availability.

2: PWM4L and PWM4H pins are available on PPS as well as dedicated.

3: SPI2 supports dedicated pins as well as PPS on 48, 64 and 80-pin devices.

4: Only 48, 64 and 80-pin devices have all eight PWM output pairs on dedicated pins. Refer to the “Pin

Diagrams” for PWM pin availability on other packages.

剩余617页未读，继续阅读

～嘟嘟～

粉丝: 0
资源: 1

dsPIC33CK256MP508 家族数据手册：高性能数字信号控制器

dsPIC33CK64MP105系列中文版数据手册（带书签）.pdf

dsPIC33CK256MP508 中文版 数据手册（带书签）

microchip dspic33ep64mc506中文资料

dsPIC33CK64MP105系列中文数据手册.pdf

dsPic33FJ64MC802-DSP-Library:dsPIC33FJ64MC802的编程功能

dsPIC33CK64MP105闪存编程技术详解

CRC控制寄存器详解 - dsPIC33CK64MP105微控制器

dsPIC33CK64MP105：特性和配置详解

dsPIC33CK64MP105系列中断控制器详解

dsPIC33CK64MP105存储器架构与程序空间详解

最新资源

dsPIC33CK256MP508 中文版数据手册（带书签）