分段量化Delta-Sigma调制器的数字噪声耦合技术解析

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"分段量化的Delta-Sigma调制器的数字噪声耦合技术" 这篇研究论文探讨了在Delta-Sigma调制器中采用分段量化技术的数字噪声耦合方法，旨在提高调制器的分辨率并减少动态元素匹配逻辑中的指数增长问题。Delta-Sigma调制器是模拟/数字转换器中常用的一种高分辨率调制技术，通过反馈噪声来提升信号质量。论文首先介绍了基本概念，Delta-Sigma（ΔΣ）调制器的工作原理是通过不断对采样值进行增量累加，然后对结果进行量化，将高分辨率的模拟信号转化为低分辨率的数字信号。这种调制方式可以实现高精度的模数转换，尤其是在噪声整形的作用下，能够有效降低量化噪声。文中提出的数字噪声耦合技术将量化器的输出分成主要部分（MSB，Most Significant Bit）和次要部分（LSB，Least Significant Bit）。MSB直接馈送到调制器输入，而LSB则被用作量化噪声，用于噪声耦合。这样的设计允许在不增加动态元素匹配逻辑复杂性的情况下，增加量化级的数量，从而提高分辨率。在数字后处理阶段，MSB和LSB被重新组合。这种策略的一个关键优势是它能保留增加量化级别带来的好处，同时避免了由于动态元素匹配导致的复杂性问题。动态元素匹配是指模拟电路中元件特性差异所引起的性能下降，这对于高精度的ΔΣ调制器来说是一个挑战。此外，通过LSB反馈引入的额外噪声整形，论文还指出这种方法能进一步减少由模拟和数字噪声传输函数不匹配造成的量化噪声泄漏。这意味着对于操作范围的限制可以更为宽松，允许更大的设计自由度，同时保持良好的信噪比。这项研究提供了一种创新的数字噪声耦合技术，可以改善Delta-Sigma调制器的性能，尤其适用于需要高分辨率和低噪声的信号处理应用，如音频编解码、通信系统和医疗成像设备等。该技术的实施有望推动高精度模拟/数字转换器的设计和发展。

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 61, NO. 6, JUNE 2014 403

Digital Noise-Coupling Technique for Delta–Sigma

Modulators With Segmented Quantization

Lin He, Member, IEEE, Yuncheng Zhang, Fang Long, Fengcheng Mei, Mingyuan Yu,

Fujiang Lin, Senior Member, IEEE , Libin Yao, Senior Member, IEEE, and Xicheng Jiang, Fellow, IEEE

Abstract—A digital noise-coupling technique for delta–sigma

modulators with a high-resolution quantizer is presented. The

proposed technique divides the outputs of the quantizer into an

MSB segment and an LSB segment. The MSBs are directly fed to

the modulator input, whereas the LSBs are used as the quantiza-

tion noise for noise coupling. After the digital postprocessing, the

MSBs and the LSBs are then recombined. As a result, it preserves

the beneﬁt of increased quantization levels without suffering from

the exponential growth of the dynamic element matching logic.

The extra noise shaping introduced by the LSB feedback further

reduces the quantization noise leakage caused by the mismatch

between the analog and digital noise transfer functions, which al-

lows a more relaxed operational ampliﬁer design. This technique is

simple to implement and well suited for low-power and wideband

applications.

Index Terms—Delta–sigma (ΔΣ), dynamic element match-

ing (DEM), digital noise coupling, large quantization level,

Leslie–Singh, low-power, noise cancelation logic, noise coupling,

segmented quantization, wideband.

I. INTRODUCTION

ELTA–sigma (ΔΣ) modulation is a typical high-

resolution analog-to-digital conversion (ADC) architec-

ture that ﬁnds wide applications in communication systems.

There is an increasing demand for low-power ΔΣ ADCs to

extend the battery lifetime. Power saving can be done either at

the system level, such as full feedforward [1], noise coupling

[2], operational ampliﬁer (op-amp) sharing [3], continuous-

time feedback [4]–[6], and double sampling [7], or at the

circuit level, such as the inverter-based structure [8]. Among

the various low-power circuit design techniques, the most

straightforward one is to increase the resolution of the multi-

bit quantizer, as it reduces the quantization noise as well

as the output signal swings of the integrators, so that the

slew rate and the gain requirement of the op-amps are re-

Manuscript received February 9, 2014; revised March 24, 2014; accepted

April 10, 2014. Date of publication April 24, 2014; date of current version

June 13, 2014. This work was supported in part by the National Natural Science

Foundation of China under Project 61204033 and in part by the Natural Science

Foundation of Jiangsu Province under Project BK2012214. This brief was

recommended by Associate Editor L. H. Corporales.

L. He, Y. Zhang, F. Long, F. Mei, M. Yu, and F. Lin are with the Micro-/

Nano-Electronic System Integration Center (MESIC), University of Science

and Technology of China, Hefei 230026, China (e-mail: helin77@ustc.edu.cn;

zhangyc23@gmail.com; longfang124@gmail.com; fchmei@mail.ustc.edu.cn;

ymyxinde@126.com; linfj@ustc.edu.cn).

L. Yao is with Kunming Institute of Physics, Kunming 650223, China

(e-mail: libin.yao@gmail.com).

X. Jiang is with Broadcom Corporation, Irvine, CA 92617 USA (e-mail:

jerry.jiang@gmail.com).

Color versions of one or more of the ﬁgures in this brief are available online

at http://ieeexplore.ieee.org.

Digital Object Identiﬁer 10.1109/TCSII.2014.2319994

laxed, which is particularly useful for scaled CMOS technol-

ogy [9]. However, increasing the resolution of a conventional

Flash quantizer requires an exponential growth of compo-

nents and power. For this reason, the resolution of most of

the Flash quantizers in a ΔΣ modulator is usually limited

to 4 bits. This problem can be partially solved by the intro-

duction of different types of quantizers, such as a two-step

quantizer [10], a pipelined quantizer [11], a synthetic aperture

radar (SAR) quantizer [12], [13], or a nonuniform quantizer

[14], [15].

However, the dynamic element matching (DEM) logic,

which dynamically shufﬂes the digital-to-analog conversion

(DAC) elements to convert their mismatch into a shaped noise,

also suffers from the exponential growth problem. Digital ΔΣ

modulation [10], [12], [16], [17] can be used to reduce the num-

ber of feedback levels. However, this digital modulation tech-

nique introduces not only an extra power but also a logic delay,

which will limit the operation frequency of the whole system.

Reference [11] directly fed back the digital outputs of the ﬁrst

pipelined stage to the modulator input to reduce the complexity

of the feedback DAC and introduced many feedback paths for

higher order noise shaping. Such an approach is complicated

and occupies a large chip area. Reference [13] adopted the

well-known Leslie–Singh architecture [18]–[20] and divided

the outputs of the quantizer into an MSB segment and an LSB

segment. The MSBs were directly fed to the modulator input,

and a digital cancelation logic was used to combine the MSBs

and the LSBs. This architecture ideally is equal to a modulator

with a high-resolution quantizer but, in practice, suffers from

the quantization noise leakage problem caused by the mis-

match between the analog and digital noise transfer functions,

which caused a measured signal-to-noise-plus-distortion ratio

(SNDR) degradation of more than 10 dB [13].

In this brief, we propose a general digital noise-coupling

technique for ΔΣ modulators with a high-resolution quantizer.

The proposed technique allows reduced feedback levels to

simplify the DEM logic. It preserves the simplicity of the

Leslie–Singh architecture to avoid the logic delay problem in

the digital modulation technique, but is much less sensitive

to the mismatch between the analog and digital noise transfer

functions. This brief is organized as follows. Section II brieﬂy

reviews the existing noise-coupling technique, the Leslie–Singh

architecture, and introduces the proposed digital noise-coupling

architecture. Section III analyzes the impact of circuit im-

perfections on the performance of the proposed architecture.

Behavioral simulations are performed to verify the analysis

using a second-order low-pass ΔΣ modulator as an example.

Section IV discusses the implementation issues. The conclusion

is provided in Section V.

IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.

See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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