CC2640R2F-Q1蓝牙模块：汽车级低功耗MCU技术规格

cc2640r2f

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CC2640R2F-Q1

ZHCSGW5A –JANUARY 2017–REVISED AUGUST 2017

www.ti.com.cn

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Product Folder Links: CC2640R2F-Q1

Table 4-1. Signal Descriptions – RGZ Package (continued)

NAME NO. TYPE DESCRIPTION

VDDS 44 Power 1.8-V to 3.8-V main chip supply

(1)

VDDS2 13 Power 1.8-V to 3.8-V DIO supply

(1)

VDDS3 22 Power 1.8-V to 3.8-V DIO supply

(1)

VDDS_DCDC 34 Power 1.8-V to 3.8-V DC/DC supply

X32K_Q1 3 Analog I/O 32-kHz crystal oscillator pin 1

X32K_Q2 4 Analog I/O 32-kHz crystal oscillator pin 2

X24M_N 46 Analog I/O 24-MHz crystal oscillator pin 1

X24M_P 47 Analog I/O 24-MHz crystal oscillator pin 2

EGP Power Ground – Exposed Ground Pad

4.3 Wettable Flanks

The automotive industry requires original equipment manufacturers (OEMs) to perform 100% automated

visual inspection (AVI) post-assembly to ensure that cars meet the current demands for safety and high

reliability. Standard quad-flat no-lead (VQFN) packages do not have solderable or exposed pins/terminals

that are easily viewed. It is therefore difficult to determine visually whether or not the package is

successfully soldered onto the printed circuit board (PCB). To resolve the issue of side-lead wetting of

leadless packaging for automotive and commercial component manufacturers, the wettable-flank process

was developed. The wettable flanks on the VQFN package provide a visual indicator of solderability and

thereby lower the inspection time and manufacturing costs.

The CC2640R2F-Q1 device is assembled using an automotive-grade VQFN package with wettable flanks.

CC2640R2F-Q1

www.ti.com.cn

ZHCSGW5A –JANUARY 2017–REVISED AUGUST 2017

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(1) All voltage values are with respect to ground, unless otherwise noted.

(2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(3) VDDS2 and VDDS3 need to be at the same potential as VDDS.

(4) Including analog-capable DIO.

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)(2)

MIN MAX UNIT

Supply voltage, VDDS

(3)

VDDR supplied by internal DC/DC regulator or

internal GLDO. VDDS_DCDC connected to VDDS on

PCB.

–0.3 4.1 V

Voltage on any digital pin

(4)

–0.3 VDDS + 0.3, max 4.1 V

Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X24M_N and X24M_P –0.3 VDDR + 0.3, max 2.25 V

Voltage on ADC input (V

)

Voltage scaling enabled –0.3 VDDS

VVoltage scaling disabled, internal reference –0.3 1.49

Voltage scaling disabled, VDDS as reference –0.3 VDDS / 2.9

Input RF level 5 dBm

stg

Storage temperature –40 150 °C

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.2 ESD Ratings

VALUE UNIT

ESD

Electrostatic discharge

Human Body Model (HBM), per AEC Q100-002

(1)(2)

All pins ±2000

Charged Device Model (CDM), per AEC Q100-011

(3)

XOCS pins 46, 47 ±250

All other pins ±500

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Ambient temperature –40 105 °C

Operating supply voltage,

VDDS

For operation in battery-powered and 3.3-V systems

(internal DC/DC can be used to minimize power consumption)

1.8 3.8 V

CC2640R2F-Q1

ZHCSGW5A –JANUARY 2017–REVISED AUGUST 2017

www.ti.com.cn

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Product Folder Links: CC2640R2F-Q1

(1) I

peri

is not supported in Standby or Shutdown.

5.4 Power Consumption Summary

Measured on the TI CC2640Q1EM-7ID reference design with T

= 25°C, V

DDS

= 3.0 V with internal DC/DC converter, unless

otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

core

Core current consumption

Reset. RESET_N pin asserted or VDDS below

power-on-reset (POR) threshold

100

Shutdown. No clocks running, no retention 150

Standby. With RTC, CPU, RAM and (partial)

1.3

µA

Standby. With RTC, CPU, RAM and (partial)

1.5

Standby. With Cache, RTC, CPU, RAM and

(partial) register retention. RCOSC_LF

3.4

Standby. With Cache, RTC, CPU, RAM and

(partial) register retention. XOSC_LF

3.6

Idle. Supply Systems and RAM powered. 650

Active. Core running CoreMark 1.45 mA + 31 µA/MHz

Radio RX 6.1

mARadio TX, 0-dBm output power 7.0

Radio TX, 5-dBm output power 9.3

Peripheral Current Consumption (Adds to core current I

core

for each peripheral unit activated)

(1)

peri

Peripheral power domain Delta current with domain enabled 20 µA

Serial power domain Delta current with domain enabled 13 µA

RF Core

Delta current with power domain enabled, clock

enabled, RF core idle

237 µA

µDMA Delta current with clock enabled, module idle 130 µA

Timers Delta current with clock enabled, module idle 113 µA

C Delta current with clock enabled, module idle 12 µA

I2S Delta current with clock enabled, module idle 36 µA

SSI Delta current with clock enabled, module idle 93 µA

UART Delta current with clock enabled, module idle 164 µA

(1) Each row is 2048 bits (or 256 bytes) wide.

(2) This number is dependent on Flash aging and will increase over time and erase cycles.

5.5 General Characteristics

= 25°C, V

DDS

= 3.0 V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

FLASH MEMORY

Supported flash erase cycles before

failure

100 k Cycles

Maximum number of write operations

per row before erase

(1)

write

operations

Flash retention 105°C 11.4

Years at

105°C

Flash page/sector erase current Average delta current 12.6 mA

Flash page/sector size 4 KB

Flash write current Average delta current, 4 bytes at a time 8.15 mA

Flash page/sector erase time

(2)

8 ms

Flash write time

(2)

4 bytes at a time 8 µs

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