嵌入式系统：PIC16F84A微控制器的代码保护特性及其挑战

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嵌入式系统中的微控制器技术是现代电子产品设计的关键组成部分，本文主要聚焦于Microchip PIC16F84A这款8位微控制器。PIC16F84A作为Microchip PICmicro家族的一员，它以其在市场上的高安全性著称，尤其是当按照制造商的规格和正常条件使用时。Microchip对其产品的安全性持有信心，但强调并非所有操作都能确保绝对安全，因为存在通过不诚实甚至非法手段突破代码保护的情况。这些方法通常涉及超出数据手册中规定的操作范围，可能涉及到知识产权的盗用。 Microchip认识到客户对于代码完整性的重要关注，并愿意与他们合作，共同面对可能的安全挑战。然而，代码保护并不是一个绝对防护措施，意味着产品并非不可破解。相反，它是一个不断发展的功能，Microchip致力于持续改进其产品的代码保护特性，以应对日益复杂的安全威胁。此数据手册详细描述了PIC16F84A的特性，包括18针增强型闪存/EEPROM，以及其作为微控制器在嵌入式应用中的性能和使用建议。用户在使用该设备时，必须自行负责确保其应用符合自身的要求，同时要注意，未经Microchip的明确书面许可，不得将Microchip的产品用于关键生命支持系统中。此外，文档还提醒读者，关于设备应用的信息仅供参考，可能会随着更新而变化。Microchip不会对信息的准确性或由此产生的专利侵权或其他知识产权问题承担责任。Microchip拥有多项注册商标，如Microchip、PIC、PICmicro、PICSTART等，使用这些商标需遵循相应的授权规定。总结来说，本资源提供了关于Microchip PIC16F84A微控制器的技术细节和安全注意事项，适用于那些在嵌入式系统开发中寻求可靠且不断进化的代码保护解决方案的工程师。在实际应用中，理解并遵守制造商的指导，合理评估风险，是确保系统安全的关键。

 2001 Microchip Technology Inc. DS35007B-page 13

PIC16F84A

3.0 DATA EEPROM MEMORY

The EEPROM data memory is readable and writable

during normal operation (full V

DD range). This memory

is not directly mapped in the register file space. Instead

it is indirectly addressed through the Special Function

Registers. There are four SFRs used to read and write

this memory. These registers are:

• EECON1

• EECON2 (not a physically implemented register)

• EEDATA

• EEADR

EEDATA holds the 8-bit data for read/write, and

EEADR holds the address of the EEPROM location

being accessed. PIC16F84A devices have 64 bytes of

data EEPROM with an address range from 0h to 3Fh.

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the new data (erase before write). The EEPROM

data memory is rated for high erase/write cycles. The

write time is controlled by an on-chip timer. The write-

time will vary with voltage and temperature as well as

from chip to chip. Please refer to AC specifications for

exact limits.

When the device is code protected, the CPU may

continue to read and write the data EEPROM memory.

The device programmer can no longer access

this memory.

Additional information on the Data EEPROM is avail-

able in the PICmicro™ Mid-Range Reference Manual

(DS33023).

U-0 U-0 U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

— — — EEIF WRERR WREN WR RD

bit 7 bit 0

bit 7-5 Unimplemented: Read as '0'

bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation is not complete or has not been started

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated

(any MCLR

Reset or any WDT Reset during normal operation)

0 = The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles

0 = Inhibits write to the EEPROM

bit 1 WR: Write Control bit

1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit

can only be set (not cleared) in software.

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not

cleared) in software.

0 = Does not initiate an EEPROM read

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F84A

DS35007B-page 14  2001 Microchip Technology Inc.

3.1 Reading the EEPROM Data

Memory

To read a data memory location, the user must write the

address to the EEADR register and then set control bit

RD (EECON1<0>). The data is available, in the very

next cycle, in the EEDATA register; therefore, it can be

read in the next instruction. EEDATA will hold this value

until another read or until it is written to by the user

(during a write operation).

EXAMPLE 3-1: DATA EEPROM READ

3.2 Writing to the EEPROM Data

Memory

To write an EEPROM data location, the user must first

write the address to the EEADR register and the data

to the EEDATA register. Then the user must follow a

specific sequence to initiate the write for each byte.

EXAMPLE 3-2: DATA EEPROM WRITE

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. We strongly

recommend that interrupts be disabled during this

code segment.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental writes

to data EEPROM due to errant (unexpected) code exe-

cution (i.e., lost programs). The user should keep the

WREN bit clear at all times, except when updating

EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will

be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. EEIF must be

cleared by software.

3.3 Write Verify

Depending on the application, good programming

practice may dictate that the value written to the Data

EEPROM should be verified (Example 3-3) to the

desired value to be written. This should be used in

applications where an EEPROM bit will be stressed

near the specification limit.

Generally, the EEPROM write failure will be a bit which

was written as a ’0’, but reads back as a ’1’ (due to

leakage off the bit).

EXAMPLE 3-3: WRITE VERIFY

TABLE 3-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

BCF STATUS, RP0 ; Bank 0

MOVLW CONFIG_ADDR ;

MOVWF EEADR ; Address to read

BSF STATUS, RP0 ; Bank 1

BSF EECON1, RD ; EE Read

BCF STATUS, RP0 ; Bank 0

MOVF EEDATA, W ; W = EEDATA

BSF STATUS, RP0 ; Bank 1

BCF INTCON, GIE ; Disable INTs.

BSF EECON1, WREN ; Enable Write

MOVLW 55h ;

MOVWF EECON2 ; Write 55h

MOVLW AAh ;

MOVWF EECON2 ; Write AAh

BSF EECON1,WR ; Set WR bit

; begin write

BSF INTCON, GIE ; Enable INTs.

Required

Sequence

BCF STATUS,RP0 ; Bank 0

: ; Any code

: ; can go here

MOVF EEDATA,W ; Must be in Bank 0

BSF STATUS,RP0 ; Bank 1

READ

BSF EECON1, RD ; YES, Read the

; value written

BCF STATUS, RP0 ; Bank 0

;

; Is the value written

; (in W reg) and

; read (in EEDATA)

; the same?

;

SUBWF EEDATA, W ;

BTFSS STATUS, Z ; Is difference 0?

GOTO WRITE_ERR ; NO, Write error

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on

all other

RESETS

08h EEDATA EEPROM Data Register

xxxx xxxx uuuu uuuu

09h EEADR EEPROM Address Register xxxx xxxx uuuu uuuu

88h EECON1

— — — EEIF WRERR WREN WR RD ---0 x000 ---0 q000

89h EECON2 EEPROM Control Register 2 ---- ---- ---- ----

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends upon condition.

Shaded cells are not used by data EEPROM.

 2001 Microchip Technology Inc. DS35007B-page 15

PIC16F84A

4.0 I/O PORTS

Some pins for these I/O ports are multiplexed with an

alternate function for the peripheral features on the

device. In general, when a peripheral is enabled, that

pin may not be used as a general purpose I/O pin.

Additional information on I/O ports may be found in the

PICmicro™ Mid-Range Reference Manual (DS33023).

4.1 PORTA and TRISA Registers

PORTA is a 5-bit wide, bi-directional port. The corre-

sponding data direction register is TRISA. Setting a

TRISA bit (= 1) will make the corresponding PORTA pin

an input (i.e., put the corresponding output driver in a

Hi-Impedance mode). Clearing a TRISA bit (= 0) will

make the corresponding PORTA pin an output (i.e., put

the contents of the output latch on the selected pin).

Reading the PORTA register reads the status of the

pins, whereas writing to it will write to the port latch. All

write operations are read-modify-write operations.

Therefore, a write to a port implies that the port pins are

read. This value is modified and then written to the port

data latch.

Pin RA4 is multiplexed with the Timer0 module clock

input to become the RA4/T0CKI pin. The RA4/T0CKI

pin is a Schmitt Trigger input and an open drain output.

All other RA port pins have TTL input levels and full

CMOS output drivers.

EXAMPLE 4-1: INITIALIZING PORTA

FIGURE 4-1: BLOCK DIAGRAM OF

PINS RA3:RA0

FIGURE 4-2: BLOCK DIAGRAM OF PIN

RA4

Note: On a Power-on Reset, these pins are con-

figured as inputs and read as '0'.

BCF STATUS, RP0 ;

CLRF PORTA ; Initialize PORTA by

; clearing output

; data latches

BSF STATUS, RP0 ; Select Bank 1

MOVLW 0x0F ; Value used to

; initialize data

; direction

MOVWF TRISA ; Set RA<3:0> as inputs

; RA4 as output

; TRISA<7:5> are always

; read as ’0’.

Data

Bus

Port

TRIS

Data Latch

TRIS Latch

RD TRIS

RD Port

TTL

Input

Buffer

VDD

I/O pin

Note: I/O pins have protection diodes to VDD and VSS.

Data

Bus

Port

TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

Input

Buffer

RA4 pin

TMR0 Clock Input

Note: I/O pins have protection diodes to VDD and VSS.

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