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JEDEC Standard No. 21C
Page 4.20.22-5
Release 22 Revision 0.31
3. Pinout and Description
Pin Description
Pin Name Description
Num-
ber
Pin Name Description
Num-
ber
CK[1:0]_t Clock Input, positive line 2
ODT[1:0]
On Die Termination Inputs 2
CK[1:0]_c Clock Input, negative line 2 DQ[31:0] Data Input/Output 32
DQS[3:0]_t Data strobes, positive line 4
CKE[1:0] Clock Enables 2 DQS[3:0]_c Data strobes, negative line 4
RAS_n Row Address Strobe 1 DM[3:0] Data Masks 4
CAS_n Column Address Strobe 1 NC No connect. May be used for future use 12
WE_n Write Enable 1
S[1:0]_n Chip Selects 2 EVENT_n
Reserved for optional hardware
temperature sensing
1
A[9:0],A11,
A[15:13]
Address Inputs 14 TEST
Memory bus test tool (Not Connected and
Not Useable on DIMMs)
1
A10/AP Address Input/Autoprecharge 1 RESET_n SDRAM control pin 1
A12/BC_n Address Input/Burst chop 1
V
DD
Power Supply 18
BA[2:0] SDRAM Bank Addresses 3
V
SS
Ground 26
SCL Serial Presence Detect (SPD) Clock Input 1
V
REF
DQ
Reference Voltage for DQ 1
SDA SPD Data Input/Output 1
V
REF
CA
Reference Voltage for CA 1
SA[2:0] SPD Address Inputs 3
V
TT
Termination Voltage 1
V
DD
SPD
SPD Power 1
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JEDEC