Actel ProASIC3E FPGA技术手册：a3pe1500

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"A3PE1500手册是关于Actel公司的ProASIC3E FPGA系列的文档，特别强调了该系列中的A3PE1500型号。该手册详细介绍了这款基于130纳米7层金属（其中6层为铜）Flash CMOS工艺的可编程闪存技术的FPGA芯片。其特性包括高容量、可重编程性、内置非易失性用户内存以及高性能和低功耗功能。" ProASIC3E Flash FPGA系列由Actel公司（现已被Microsemi收购）推出，A3PE1500是该系列中的一员，具备一系列显著特点。首先，它提供了高容量的设计选项，系统门数量范围从600k到3百万，同时集成有108到504k位的真双端口SRAM，以及最多620个用户I/O引脚。这使得A3PE1500适合于需要大量逻辑资源和高速存储的复杂系统设计。采用130纳米的工艺技术，A3PE1500支持Live-at-Power-Up (LAPU) Level 0功能，这意味着在上电时FPGA可以立即开始工作。作为单芯片解决方案，它能够在电源关闭时保留已编程设计，确保了设计的稳定性和可靠性。在性能方面，A3PE1500能实现350MHz的系统性能，支持3.3V, 66MHz的64位PCI接口。此外，它还包含1kbit的Flash ROM，提供同步接口，用于存储关键配置数据或固件。为了满足现场可编程的需求，A3PE1500支持In-System Programming (ISP)，并具有安全特性。通过JTAG（遵循IEEE1532标准）接口，利用内置的128位高级加密标准（AES）解密进行安全的ISP。同时，FlashLock功能可以保护FPGA内容不被非法访问或修改。在功耗优化上，A3PE1500支持核心电压降低以降低功耗，并且适用于1.5V的系统。其低阻抗闪存开关设计进一步降低了能耗。高性能路由层次结构是A3PE1500的另一大亮点，包括分段化的层次化路由和时钟结构、超快速本地和长线网络、增强的高速非常长线网络以及高性能低时延全局网络。这样的架构设计使芯片能够处理超高速的应用场景。总而言之，A3PE1500是一款面向高性能、低功耗应用的先进FPGA，其丰富的资源和安全特性使其成为嵌入式系统和工业控制等领域中的理想选择。

ProASIC3E DC and Switching Characteristics

2-4 v1.2

PLL Behavior at Brownout Condition

Actel recommends using monotonic power supplies or voltage regulators to ensure proper

power-up behavior. Power ramp-up should be monotonic at least until V

and V

CCPLXL

exceed

brownout activation levels. The V

activation level is specified as 1.1 V worst-case (see Figure 2-1

on page 2-4 for more details).

When PLL power supply voltage and/or V

levels drop below the V

brownout levels (0.75 V ±

0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the

Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information

on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

Figure 2-1 • I/O State as a Function of V

CCI

and V

Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because V

CCI

are below

specification. For the same reason, input

buffers do not meet V

levels, and

output buffers do not meet V

levels.

Min V

CCI

datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

= 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

= 0.85 V ± 0.25 V

Deactivation trip point:

= 0.75 V ± 0.25 V

Activation trip point:

= 0.9 V ± 0.3 V

Deactivation trip point:

= 0.8 V ± 0.3 V

= 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, V

, V

, etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because V

CCI

below specification. For the

same reason, input buffers do not

meet V

levels, and output

buffers do not meet V

levels.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

CCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the V

is below specification.

= V

CCI

+ VT

ProASIC3E DC and Switching Characteristics

v1.2 2-5

Thermal Characteristics

Introduction

The temperature variable in Actel Designer software refers to the junction temperature, not the

ambient temperature. This is an important distinction because dynamic and static power

consumption cause the chip junction to be higher than the ambient temperature.

EQ 2-1 can be used to calculate junction temperature.

= Junction Temperature = ΔT + T

EQ 2-1

where:

= Ambient Temperature

ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θ

* P

= Junction-to-ambient of the package. θ

numbers are located in Table 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θ

and the junction-to-ambient air thermal

resistivity is θ

. The thermal characteristics for θ

are shown for two air flow rates. The absolute

maximum junction temperature is 110°C. EQ 2-2 shows a sample calculation of the absolute

maximum power dissipation allowed for an 896-pin FBGA package at commercial temperature and

in still air.

EQ 2-2

Temperature and Voltage Derating Factors

Maximum Power Allowed

Max. junction temp. (°C) Max. ambient temp. (°C)–

(°C/W)

---------------------------------------------------------------------------------------------------------------------------------------

110°C70°C–

13.6°C/W

------------------------------------ 5 . 8 8 W===

Table 2-5 • Package Thermal Resistivities

Package Type Pin Count θ

UnitsStill Air 200 ft./min. 500 ft./min.

Plastic Quad Flat Package (PQFP) 208 8.0 26.1 22.5 20.8 C/W

Plastic Quad Flat Package (PQFP) with

embedded heat spreader

208 3.8 16.2 13.3 11.9 C/W

Fine Pitch Ball Grid Array (FBGA) 256 3.8 26.9 22.8 21.5 C/W

484 3.2 20.5 17.0 15.9 C/W

676 3.2 16.4 13.0 12.0 C/W

896 2.4 13.6 10.4 9.4 C/W

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T

= 70°C, V

=1.425V)

Array Voltage

(V)

Junction Temperature (°C)

–40°C 0°C 25°C 70°C 85°C 100°C

1.4250.870.920.951.001.021.05

1.5000.830.880.900.950.971.00

1.5750.800.850.870.920.940.96

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