高性能锗量子阱场效应晶体管：低功耗(0.5V)III-V CMOS技术的P通道选项

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"这篇文档是关于使用锗作为p通道量子阱场效应晶体管（QWFET）的研究，作为低功耗（Vcc=0.5V）III-V CMOS架构的一种选择。研究中展示了具有14.5 Å栅氧化层厚度和770 cm²/V·s载流子迁移率的锗p通道QWFET，这在5x10¹² cm⁻²的电荷密度下（在0.5V工作电压下最先进的硅晶体管通道）表现卓越。对于小于40 Å的薄栅氧化层，这是迄今为止报道的锗器件中最高的空穴迁移率，比最先进的应变硅高出4倍。QWFET架构通过引入双轴应变并消除掺杂剂杂质散射来实现高迁移率。采用硅帽和低界面态密度的晶体管工艺实现了薄栅氧化层。同时，通过磷结层抑制SiGe缓冲层中的并联导电，从而允许健康的亚阈值行为。" 文章详细讨论了使用锗作为半导体材料在构建高性能p通道量子阱场效应晶体管（QWFET）上的潜力。锗作为一种半导体元素，因其特殊的化学和物理特性，如与氧气和氢气的反应性、在特定温度下的氧化行为以及与同族元素类似的化学性质，使其在半导体领域具有重要应用。在本文档中，研究人员着重强调了锗在低功耗电路设计中的作用，特别是在0.5V工作电压下的III-V CMOS架构。锗p通道QWFET的设计利用了双轴应变技术，这种技术可以显著提高载流子（在这种情况下为空穴）的迁移率。迁移率的提高意味着电子在材料中移动更快，因此晶体管的开关性能更优，能效更高。此外，通过采用薄的栅氧化层（14.5 Å），研究人员能够实现前所未有的高迁移率，这是由于减少了掺杂剂杂质对电子运动的干扰。值得注意的是，这种薄栅氧化层的实现依赖于先进的工艺技术，包括硅帽和低界面态密度的晶体管制造过程。为了优化设备性能，研究者还通过磷结层解决了SiGe缓冲层中的并联导电问题。这一创新措施有助于防止不必要的电流泄露，进一步改善了晶体管的亚阈值行为，这对于低功耗电路至关重要。整体而言，这些研究成果为发展高效、低功耗的锗基半导体设备提供了新的方向和可能，尤其是在未来的微电子和纳米电子学领域。

High Mobility Strained Germanium Quantum Well Field Effect Transistor

as the P-Channel Device Option for Low Power (Vcc = 0.5 V) III-V CMOS Architecture

R. Pillarisetty, B. Chu-Kung, S. Corcoran, G. Dewey, J. Kavalieros, H. Kennel, R. Kotlyar, V. Le,

D. Lionberger, M. Metz, N. Mukherjee, J. Nah, W. Rachmady, M. Radosavljevic, U. Shah, S. Taft, H. Then,

N. Zelick, and R Chau

Intel Corporation, Technology and Manufacturing Group, Hillsboro, OR 97124, USA

Abstract

In this article we demonstrate a Ge p-channel QWFET with

scaled TOXE = 14.5Å and mobility of 770 cm

/V*s at n

=5x10

-2

(charge density in the state-of-the-art Si transistor channel at

Vcc = 0.5V). For thin TOXE < 40 Å, this represents the highest

hole mobility reported for any Ge device and is 4x higher than

state-of-the-art strained silicon. The QWFET architecture

achieves high mobility by incorporating biaxial strain and

eliminating dopant impurity scattering. The thin TOXE was

achieved using a Si cap and a low Dt transistor process, which

has a low oxide interface Dit. Parallel conduction in the SiGe

buffer was suppressed using a phosphorus junction layer,

allowing healthy subthreshold slope in Ge QWFET for the first

time. The Ge QWFET achieves an intrinsic Gmsat which is 2x

higher than the InSb p-channel QWFET. These results suggest

the Ge QWFET is a viable p-channel option for non-silicon

CMOS.

Introduction

Recently, III-V quantum well field effect transistor (QWFET)

research for future low power CMOS logic applications has

made significant progress [1,3]. While n-channel III-V studies

have shown significant drive current gains over state of the art

silicon at low Vcc [1], the corresponding p-channel transistor

with thin TOXE and high mobility (µ) has not yet been

demonstrated. In this study, we demonstrate a high mobility

strained germanium (Ge) p-channel QWFET suitable for low

power CMOS architecture with scaled TOXE = 14.5Å and hole

mobility = 770 cm

/V*s at n

=5x10

-2

For TOXE < 40 Å,

this represents the highest hole mobility reported for any Ge

device and is 4x higher than state-of-the-art strained silicon.

These results suggest that the Ge QWFET is a viable p-channel

option for III-V CMOS realization.

Materials Growth and Device Fabrication

Figure 1 shows a schematic of a biaxially strained undoped Ge

QW structure. The boron modulation doping layer allows for

Hall measurement, but is optional for implanted S/D transistors.

The phosphorus doped layer is grown to suppress parallel

conduction in the SiGe buffers. A cross sectional TEM image of

a Ge QW grown by RTCVD on 300mm silicon is shown in Fig

2, highlighting both the 2-step SiGe buffer layers and biaxially

strained Ge QW layer bounded by Si

barriers. Although not

shown, we also grew relaxed Ge layers on this two layer buffer

to provide us with a Ge MOSFET reference structure. Figure 3

shows X-ray diffraction spectra of the symmetric (004) reflection

for both the Ge QW and relaxed Ge structures indicating 1.3%

biaxial strain in the Ge QW. The Hall mobility for RTCVD

grown Ge QW structures, plotted in Fig 4, matches MBE grown

Ge QW literature data [5-7] and shows gain over the InSb QW[3]

and strained Si [2]. Figure 5 shows a TEM of a fully processed

Ge QWFET utilizing shallow trench isolation (not shown),

HfO

/TiN high-k metal gate, self-aligned B-implanted S/D, W/Ti

contacts, a strained Ge QW channel, and a phosphorus isolation

layer. A TEM image of a Ge QWFET with an in-situ doped

1-x

raised source/drain (RSD) is shown in Fig 6.

Silicon Cap and Gate Dielectric Interface

A thin Si cap layer is required to prevent carrier spill-out from

the Ge QW. This is demonstrated in Fig 7 where k*p-Poisson

simulations show that for a hole density (n

)

= 5x10

-2

10Å Si cap layer confines carriers in the Ge QW, whereas

significant carrier spill-out occurs with a 100Å Si

barrier.

Figure 8 shows a TEM image of a high-k metal gate stack with a

thin silicon cap on a Ge QW. Part of the silicon cap is oxidized

due to thermal cycle (Dt) during the transistor fabrication

process. This is suggested by the EDS depth profile of the gate

stack, shown in Fig 9, indicating the presence of both Si and SiO

between the Ge and HfO

. CV data in Fig 10 indicates inversion

TOXE reduction with Si cap thickness scaling. Due to

asymmetry of the valence and conduction band offsets between

Si and Ge, the Si cap only contributes to C

inv

. Hence, the SiO

thickness (T

SiO2

) on the Si cap can be extracted from the

accumulation TOXE, and in this example is 6Å for all cases due

to constant thermal Dt. Since a body contact is needed to

measure the accumulation CV, this data was collected from the

Ge MOSFET reference device. The corresponding µ vs n

plotted

in Fig 11 shows that µ improves as Si cap thickness is reduced

due to reduction in carrier spill-out. However, µ is degraded

significantly without Si cap due to an increase in interface trap

density (Dit). Figure 12 shows that by lowering process Dt from

700°C to 635°C TOXE can scale to 14.5Å without loss of

mobility via T

SiO2

reduction on the Si cap.

Ge QWFET Device Analysis

The minimal CV frequency dispersion in Fig 13 indicates a good

quality interface for both the relaxed Ge MOSFET reference and

strained Ge QWFET with the same 14.5Å TOXE process. Figure

14 shows mobility vs n

for both devices. The experiments agree

with k*p simulations, which assume Dit and surface roughness

matched to state-of-the-art Si. This indicates a high quality oxide

interface on Ge. At n

= 5x10

-2

, the QWFET exhibits 4x

mobility gain over state-of-the-art strained Si [2]. Furthermore, in

Fig 15 the Ge QWFET achieves the highest mobility (770

/V*s) at the thinnest TOXE (14.5Å) compared to the best Ge

devices in literature [8-9]. Figs 16 and 17 plot the temperature

(T) dependence of the Ge QWFET mobility, which shows no

saturation of µ down to T=20K. This indicates minimal impact

from Coulomb scattering due to absence of doping in the QW

and low Dit.

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