NM1820 Series Data Sheet
Preliminary
Sept 19, 2016 Page 5 of 23 Rev. 0.7
2 FEATURES
Operation Supply Voltage VIN Range from 4.5 to 30V
Gate Driver (half-bridge gate drive)
3 low-side and 3 high-side gate drivers
More than 0.6A gate driving capability
UVLO(Under voltage lockout=4.1V) function to disable PWM output (PWM
output low)
Embedded two Internal 5V voltage regulators with 35mA driving capability
Matched propagation delay of around 500ns for both PWM complementary
channels
PWM output delay matching < 50 ns
Max V
GS
of Power MOS is up to 5V
Thermal shutdown circuitry to limit the junction temperature at 125 ℃
MCU Core
ARM
®
Cortex™-M0 core running up to 48 MHz
One 24-bit system timer
Supports Low Power Sleep mode
A single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-level of priority
Supports Serial Wire Debug (SWD) interface and two watch points/four
breakpoints
Hardware Divider
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends
to 32-bit)
Divided by zero warning flag
6 HCLK clocks taken for one cycle calculation
Waiting for calculation ready automatically when reading quotient and remainder
Memory
17.5 KB Flash memory for program memory (APROM)
Configurable Flash memory for data memory (Data Flash)
2 KB Flash for loader (LDROM)
2 KB SRAM for internal scratch-pad RAM (SRAM)
Clock Control
48 MHz internal oscillator (HIRC) (±1% accuracy at 25
O
C, 5V)
Dynamically calibrating the HIRC OSC to 48 MHz ±2% from -40
O
C to 105
O
C
by external 32.768K crystal oscillator (LXT)