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瑞萨C1MAx芯片手册：RH850G3MH高性能软件应用指南

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瑞萨C1MAx芯片应用手册 - 软件版，针对的是RH850G3MH这款32位RISC微控制器，它是RH850G3M系列的一员，但具有更高的性能表现。该手册主要面向用户，提供详细的技术指导，旨在帮助用户理解并应用RH850G3MH的硬件电路、软件设计以及相关技术细节。手册的发布日期为2016年12月，版本为1.30，强调所有信息仅在发布时有效，可能会根据Renesas Electronics Corp.的更新而有所变动，因此建议用户通过Renesas官方网站或其他官方渠道获取最新资料。手册内容包括了对电路设计、软件编程和应用示例的描述，这些信息主要用于展示半导体产品的操作原理和功能展示，但使用者需自行承担将这些电路、软件及其信息融入设备设计的责任。Renesas Electronics强调，虽然他们在准备文档时已尽合理注意，但不对其提供的信息导致的任何损失或第三方损失承担责任。用户在使用这份手册时，应注意遵守版权和许可协议，确保遵循制造商的指导，进行适当的测试和验证，以确保产品的安全性和性能。同时，手册中可能涉及的开发工具、编程接口和调试方法也应按照文档中的步骤来操作，以充分利用RH850G3MH芯片的优势。瑞萨C1MAx芯片应用手册是一份重要的参考资料，它不仅提供了产品特性和工作原理，还为开发者提供了实际应用的案例和最佳实践，有助于提升用户的开发效率和产品质量。在实际应用过程中，务必密切关注Renesas Electronics的最新更新，以确保始终与产品的最新规格保持同步。

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RH850G3MH Software Section 2　PROCESSOR MODEL

R01US0143EJ0130 Rev.1.30 Page 16 of 426

Dec 22, 2016

2.3 Exceptions and Interrupts

Exceptions and interrupts are exceptional events that cause the program under execution to branch to

another program. Exceptions and interrupts are triggered by various sources, including interrupts from

peripherals and program abnormalities.

For details, see Section 4, EXCEPTIONS AND INTERRUPTS.

2.3.1 Exception Level

In this CPU, if an exception with a high degree of urgency occurs while another exception is being

processed, the urgent exception will be processed by priority. To make it possible to return to the

interrupted exception handling after acknowledging the urgent exception, even if the context had not

been saved to the memory, exception causes are managed in the following two hierarchical levels.

 EI level exception

 FE level exception

EI level exceptions are used for processing such as regular user processing, interrupt servicing, and OS

processing. FE level exceptions are used to enable interrupts with a high degree of urgency for the

system or exceptions from the memory management function that might occur during OS processing to

be acknowledged even while an EI level exception is being processed.

RH850G3MH Software Section 2　PROCESSOR MODEL

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Dec 22, 2016

2.4 Coprocessors

In this CPU, single-precision and double-precision FPU expansion functions are incorporated.

2.4.1 Coprocessor Use Permissions

To execute a coprocessor instruction or defined opcode processing, permission to use the

corresponding coprocessor instruction is necessary. Coprocessor use permissions are specified by the

PSW.CU2 to PSW.CU0 bits, and, if an attempt is made to execute an instruction for which the

corresponding coprocessor use permission is cleared to 0, a coprocessor unusable exception (UCPOP)

occurs.

2.4.2 Correspondences between Coprocessor Use Permissions and

Coprocessors

This CPU defines coprocessor use permissions to control the availability of the coprocessor for each

program during CPU operation. There are three coprocessor use permissions (CU0 to CU2), and their

correspondences with the coprocessors are shown in the following table.

2.4.3 Coprocessor Unusable Exceptions

A coprocessor unusable exception occurs if an attempt is made to execute a coprocessor instruction or

access a system register of the coprocessor without having the corresponding coprocessor use

permission (PSW.CUn = 0).

2.4.4 System Registers

Some coprocessor functions are defined by system registers. The coprocessor use permission is

necessary to access the system register of a coprocessor function. For some system registers, the

supervisor privilege (SV permission) is necessary in addition to the coprocessor use permission.

For details about the permissions necessary to access system registers, see Section 2.5, Registers.

Table 2.2 Correspondences Between Coprocessor Use Permissions and Coprocessors

Coprocessor Use Permission Coprocessor Function Exception Cause Code

CU0 Single-precision FPU expansion

function

Double-precision FPU expansion

function

CU1 Reserved 81

CU2 Reserved 82

RH850G3MH Software Section 2　PROCESSOR MODEL

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Dec 22, 2016

2.5 Registers

This CPU defines program registers (general-purpose registers and the program counter PC) and

system registers for controlling the status and storing exception information.

2.5.1 Program Registers

The program registers include general-purpose registers (r0 to r31) and the program counter (PC).

Note: UM: User register. This register can always be accessed because no access permission is required.

2.5.2 System Registers

For details about program registers, see Section 3.1, Program Registers.

Group numbers 0 to 3 : Registers related to basic functions

Group numbers 4 to 7 : Registers related to the memory management function

Group numbers 12 to 15 : Registers defined in the CPU hardware specifications

Group numbers 16 and later : Reserved for future expansion

For details about system registers, see the relevant sections in Section 3, REGISTER SET.

2.5.3 Register Updating

There are several methods used to update registers. Normally, no particular restrictions apply when

updating register by using an instruction. However, when updating registers by using the following

instructions, some restrictions might apply, depending on the operating mode.

 LDSR

 STSR

Table 2.3 Program Registers

Category Access Permission Name

Program counter UM PC

General-purpose registers UM r0 to r31

RH850G3MH Software Section 2　PROCESSOR MODEL

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Dec 22, 2016

(1) LDSR and STSR

The LDSR and STSR instructions can access all the system registers. However, If a system register is

accessed without the proper permission, a PIE exception or UCPOP exception might occur. For details

about the access permission for each register, see the description of system registers in Section 3,

CPU Operating Modes and Privileges.

Figure 2.3 shows the flow of executing the LDSR and STSR instructions.

Figure 2.3 Flow of Executing the LDSR and STSR Instructions

Execution of an instruction starts

Are the terminating

exception acknowledgment

conditions satisfied?

Reflect operation results

(register/memory/

PC update, etc.)

Execution of the next

instruction starts

Exception transition processing

(register/PC update, etc.)

Execute register access

Yes (any exception)

Is this an undefined

as undefined?)

Execute operation

Is the access permission

CUn, and PSW.CUn = 0?

Yes (UCPOP exception)

Is the access permission SV

and PSW.UM = 1?

Yes (PIE exception)

Yes

The read result is undefined

or write is ignored

RH850G3MH Software Section 2　PROCESSOR MODEL

R01US0143EJ0130 Rev.1.30 Page 20 of 426

Dec 22, 2016

2.5.4 Accessing Undefined Registers

If a system register number without any register assigned is accessed or if an inaccessible register is

accessed, the following results occur.

 Undefined registers are handled as having the SV permission. When they are accessed by an

LDSR or STSR instruction in user mode (PSW.UM = 1), a PIE exception occurs.

 For a read operation, the read result is undefined. If the read value is used in a program,

unexpected behaviors might occur.

 For a write operation, the write operation is ignored.

However, writing to the following system register numbers is prohibited.

Writing prohibited: [SR11, 0], [SR1, 1], [SR7, 1], [SR10, 1], [SR13, 1], [SR14, 1], [SR15, 1],

[SR16, 1], [SR5, 2], [SR20, 5]

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