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X2000 IoT应用处理器编程手册
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"X2000 IoT Application Processor Programming Manual Release Date: Jan 17, 2020"
本文档是Ingenic Semiconductor公司为X2000物联网应用处理器提供的编程手册,适用于2020年2月19日。X2000是一款专为物联网(IoT)应用设计的处理器,它可能包含了高性能的计算核心、低功耗特性以及针对物联网环境优化的各种接口。
### X2000 IoT应用处理器概述
X2000 IoT应用处理器可能集成了以下关键特性:
1. **多核CPU**: 可能包括多个CPU核心,支持多任务并行处理,优化了性能与能效。
2. **嵌入式存储**: 集成高速内存,如DDR,以满足实时数据处理的需求。
3. **低功耗设计**: 采用节能技术,适合长时间运行的物联网设备。
4. **丰富的外设接口**: 如GPIO、I2C、SPI、UART、USB、以太网等,便于连接各种传感器和外围设备。
5. **嵌入式操作系统支持**: 支持Linux等开源操作系统,为开发者提供丰富的软件生态和开发工具。
6. **硬件加速器**: 可能包含加密/解密、图像处理、AI运算等加速单元,提升特定任务的处理速度。
### Linux编程和开发
由于标签中提到"Linux",这份文档将详细阐述如何在X2000处理器上使用和定制Linux系统。这可能包括:
1. **内核配置和编译**: 如何根据X2000的硬件特性定制Linux内核。
2. **驱动程序开发**: 为X2000的特定外设编写和集成驱动程序。
3. **文件系统构建**: 如何创建和优化适合物联网设备的文件系统。
4. **设备树配置**: 使用设备树来描述硬件结构,使操作系统更好地适配硬件。
5. **电源管理**: 针对物联网设备的低功耗需求,进行电源管理和休眠模式的配置。
6. **安全性和固件更新**: 实现安全启动、远程固件更新机制,确保设备的安全性。
### 注意事项和法律声明
Ingenic Semiconductors明确指出,该文档仅用于其产品,未授予任何知识产权许可。使用该处理器进行设计时,用户需自行承担风险,公司不提供任何明示或暗示的保证,特别是关于医疗或生命维持设备的用途。所有信息均以初步状态提供,可能会随时更改,使用者应时刻关注最新的文档和错误更正。
X2000 IoT应用处理器编程手册是开发人员和系统工程师深入理解、开发和优化基于X2000处理器的物联网设备的重要参考资料。通过这份文档,开发者可以学习如何利用Linux操作系统充分发挥X2000的性能,同时遵循最佳实践来确保设备的安全性和稳定性。
CONTENTS
xiv
X2000 IoT Application Processor Programming Manual
Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
23.6.1 DMA Control ................................................................................................................. 632
23.6.2 DMA Interrupt Pending (DIRQP).................................................................................. 633
23.6.3 DMA Doorbell (DDB) .................................................................................................... 634
23.6.4 DMA Doorbell Set (DDS) ............................................................................................. 634
23.6.5 Descriptor Interrupt Pending (DIP) .............................................................................. 634
23.6.6 Descriptor Interrupt Clear (DIC) ................................................................................... 635
23.6.7 DMA Channel Programmable (DMACP) ..................................................................... 635
23.6.8 DMA Soft IRQ Pending (DSIRQP) ............................................................................... 635
23.6.9 DMA Soft IRQ Mask (DSIRQM) ................................................................................... 636
23.6.10 DMA Channel IRQ Pending to MCU (DCIRQP) ...................................................... 636
23.6.11 DMA Channel IRQ to MCU Mask (DCIRQM) .......................................................... 637
23.6.12 Programmable Channel Bound With INTC_IRQ ..................................................... 637
23.6.13 Special Channel 0 and Channel 1 ........................................................................... 637
23.7 MCU .................................................................................................................................... 638
23.7.1 MCU Control & Status ................................................................................................. 638
23.7.2 MCU Normal MailBox .................................................................................................. 639
23.7.3 MCU Security MailBox ................................................................................................. 639
23.7.4 MCU Interrupt .............................................................................................................. 639
23.7.5 Multiple Bank Tightly Coupled Sharing Memory .......................................................... 640
23.7.6 CP0 Registers of MCU ................................................................................................ 640
23.7.7 Normal Exceptions Accepted by MCU ......................................................................... 641
23.7.8 How to Boot MCU Up .................................................................................................. 641
23.7.9 Security features .......................................................................................................... 642
23.8 DMA manipulation ............................................................................................................... 642
23.8.1 Descriptor Transfer Mode ............................................................................................ 642
23.8.2 No-Descriptor Transfer Mode ...................................................................................... 645
23.8.3 Descriptor Transfer Interrupt/Stop control ................................................................... 645
23.9 DMA Requests..................................................................................................................... 647
23.9.1 Auto Request ............................................................................................................... 647
23.9.2 On-Chip Peripheral Request ........................................................................................ 647
23.10 How to Use Programmable DMA Channel .......................................................................... 647
24 SAR A/D Controller ......................................................................... 648
24.1 Overview .............................................................................................................................. 648
24.2 Features .............................................................................................................................. 648
24.3 Block Diagram ..................................................................................................................... 648
24.4 Pins Description................................................................................................................... 649
24.5 Register Description ............................................................................................................ 649
24.5.1 Register Memory Map ................................................................................................. 649
24.5.2 Register and Fields Description ................................................................................... 650
24.6 SAR A/D Controller Guide ................................................................................................... 655
24.6.1 Power Down Mode ...................................................................................................... 656
24.6.2 AUX Sample Operation ............................................................................................... 656
CONTENTS
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X2000 IoT Application Processor Programming Manual
Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
25 Real Time Clock ............................................................................. 657
25.1 Overview ............................................................................................................................. 657
25.2 Features .............................................................................................................................. 657
25.3 Block Diagram ..................................................................................................................... 657
25.4 Pins Description .................................................................................................................. 658
25.5 Registers Description .......................................................................................................... 658
25.5.1 RTC Control Register (RTCCR) .................................................................................. 660
25.5.2 RTC Second Register (RTCSR) .................................................................................. 661
25.5.3 RTC Second Alarm Register (RTCSAR) ..................................................................... 662
25.5.4 RTC Regulator Register (RTCGR) .............................................................................. 662
25.5.5 Hibernate Control Register (HCR) .............................................................................. 663
25.5.6 HIBERNATE mode Wakeup Filter Counter Register (HWFCR) .................................. 664
25.5.7 Hibernate Reset Counter Register (HRCR) ................................................................ 664
25.5.8 HIBERNATE Wakeup Control Register (HWCR) ........................................................ 665
25.5.9 HIBERNATE Wakeup Status Register (HWRSR) ....................................................... 665
25.5.10 Hibernate Scratch Pattern Register (HSPR) ........................................................... 666
25.5.11 Write Enable Pattern Register (WENR) .................................................................. 667
25.5.12 WKUP_PIN_RST control register (WKUPPINCR) .................................................. 668
25.6 Operation Flow .................................................................................................................... 668
25.6.1 Registers Access ......................................................................................................... 668
25.6.2 Registers Read ............................................................................................................ 668
25.6.3 Registers Write ............................................................................................................ 669
25.6.4 Normal Mode ............................................................................................................... 669
25.6.5 Power Detect ............................................................................................................... 669
25.6.6 Power On Timing Diagram .......................................................................................... 669
25.6.7 HIBERNATE Mode ...................................................................................................... 669
25.6.8 Procedure to Enter HIBERNATE mode ....................................................................... 670
25.6.9 Procedure to Wake-up from HIBERNATE mode ......................................................... 670
25.6.10 Time Regulation ....................................................................................................... 670
25.6.11 Clock select ............................................................................................................. 671
26 EFUSE Slave Interface (EFUSE) .................................................. 673
26.1 Overview ............................................................................................................................. 673
26.2 Registers ............................................................................................................................. 673
26.2.1 Registers Memory Map ............................................................................................... 674
26.2.2 Registers and Fields Description ................................................................................ 674
26.3 Operation Mode .................................................................................................................. 679
26.4 Flow ..................................................................................................................................... 680
26.4.1 Program EFUSE Flow ................................................................................................. 680
26.4.2 Program Security Key Flow ......................................................................................... 680
26.4.3 Read EFUSE Flow ...................................................................................................... 681
26.4.4 Read Security Key Flow .............................................................................................. 681
CONTENTS
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X2000 IoT Application Processor Programming Manual
Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
PERIPHERALS .................................................................................... 682
27 General-Purpose I/O Ports ............................................................. 683
27.1 Overview .............................................................................................................................. 683
27.2 Features .............................................................................................................................. 683
27.3 About GPIO Port Summary Table ....................................................................................... 683
27.3.1 GPIO Port A Summary ................................................................................................. 686
27.3.2 GPIO Port B Summary ................................................................................................ 687
27.3.3 GPIO Port C Summary ................................................................................................ 688
27.3.4 GPIO Port D Summary ................................................................................................ 689
27.3.5 GPIO Port E Summary ................................................................................................ 690
27.3.6 GPIO Port Z - Shadow Group ...................................................................................... 692
27.4 Registers Description .......................................................................................................... 692
27.4.1 Register Memory Map ................................................................................................. 692
27.4.2 Register and Fields Description ................................................................................... 698
27.4.3 PORT PIN Level Registers (PxPINL,0x0000) ............................................................. 698
27.4.4 PORT Interrupt Registers (PxINT,0x0010) .................................................................. 699
27.4.5 PORT Interrupt Set Registers (PxINTS,0x0014) ......................................................... 699
27.4.6 PORT Interrupt Clear Registers (PxINTC,0x0018) ...................................................... 699
27.4.7 PORT Mask Registers (PxMSK,0x0020) ..................................................................... 700
27.4.8 PORT Mask Set Registers (PxMSKS,0x0024) ............................................................ 700
27.4.9 PORT Mask Clear Registers (PxMSKC,0x0028) ........................................................ 701
27.4.10 PORT PAT1/Direction Registers (PxPAT1,0x0030) ................................................. 701
27.4.11 PORT PAT1/Direction Set Registers (PxPAT1S,0x0034) ........................................ 702
27.4.12 PORT PAT1/Direction Clear Registers (PxPAT1C,0x0038) ..................................... 702
27.4.13 PORT PAT0/Data Registers (PxPAT0,0x0040) ........................................................ 703
27.4.14 PORT PAT0/Data Set Registers (PxPAT0S,0x0044) ............................................... 703
27.4.15 PORT PAT0/Data Clear Registers (PxPAT0C,0x0048) ........................................... 704
27.4.16 PORT FLAG Registers (PxFLG,0x0050) ................................................................. 704
27.4.17 PORT FLAG Clear Registers (PxFLGC,0x0058) ..................................................... 705
27.4.18 PORT Dual-Edge Interrupt Register (PxEDG,0x70) ................................................ 705
27.4.19 PORT Dual-Edge Interrupt Set Register (PxEDGS,0x74) ....................................... 706
27.4.20 PORT Dual-Edge Interrupt Clear Register (PxEDGC,0x78) .................................... 706
27.4.21 PORT PULL-UP State Register (PxPU,0x80) .......................................................... 706
27.4.22 PORT PULL-UP State Set Register (PxPUS,0x84) ................................................. 708
27.4.23 PORT PULL-UP State Clear Register (PxPUC,0x88) ............................................. 709
27.4.24 PORT PULL-DOWN State Register (PxPD,0x90) ................................................... 709
27.4.25 PORT PULL-DOWN State Set Register (PxPDS,0x94) .......................................... 711
27.4.26 PORT PULL-DOWN State Clear Register (PxPDC,0x98) ....................................... 711
27.4.27 PORT Drive Strength State Register0 (PxDS0,0xA0) ............................................. 711
27.4.28 PORT Drive Strength State Set Register0 (PxDS0S,0xA4) .................................... 712
27.4.29 PORT Drive Strength State Clear Register0 (PxDS0C,0xA8) ................................. 712
CONTENTS
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X2000 IoT Application Processor Programming Manual
Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
27.4.30 PORT Drive Strength State Register1 (PxDS1,0xB0) ............................................. 713
27.4.31 PORT Drive Strength State Set Register1 (PxDS1S,0xB4) .................................... 713
27.4.32 PORT Drive Strength State Clear Register1 (PxDS1C,0xB8) ................................ 713
27.4.33 PORT Drive Strength State Register2 (PxDS2,0xC0) ............................................. 714
27.4.34 PORT Drive Strength State Set Register2 (PxDS2S,0xC4) .................................... 714
27.4.35 PORT Drive Strength State Clear Register2 (PxDS2C,0xC8) ................................ 715
27.4.36 PORT Slew Rate Register (PxSR,0xD0) ................................................................. 715
27.4.37 PORT Slew Rate Set Register (PxSRS,0xD4) ........................................................ 715
27.4.38 PORT Slew Rate Clear Register (PxSRC,0xD8) .................................................... 716
27.4.39 PORT Schmitt Trigger Register (PxSMT,0xE0) ....................................................... 716
27.4.40 PORT Schmitt Trigger Set Register (PxSMTS,0xE4) .............................................. 716
27.4.41 PORT Schmitt Trigger Clear Register (PxSMTC,0xE8) .......................................... 717
27.4.42 PORT Z Shadow Register Group ............................................................................ 717
27.4.43 GPIOZ Group ID to Load Register (PzGID2LD,0x00F0) ........................................ 719
27.5 Program Guide .................................................................................................................... 720
27.5.1 Port Function Guide .................................................................................................... 720
27.5.2 Configure without 3rd-unexpected state ..................................................................... 720
27.5.3 Dual-edge Interrupt Configure Guide .......................................................................... 721
28 SMB Controller .............................................................................. 722
28.1 Overview ............................................................................................................................. 722
28.1.1 Features ...................................................................................................................... 722
28.1.2 Pin Description ............................................................................................................ 722
28.2 Registers ............................................................................................................................. 723
28.2.1 Registers Memory Map ............................................................................................... 723
28.2.2 Registers and Fields Description ................................................................................ 724
28.2.3 SMB_CON (SMB Control Register) ............................................................................ 724
28.2.4 SMB_TAR (SMB Target Address Register) ................................................................. 725
28.2.5 SMB_SAR (SMB Slave Address Register) ................................................................. 727
28.2.6 SMB_HS_MADDR (SMB High Speed Master Mode Code Address Register) ........... 727
28.2.7 SMB_DC (SMB Rx/Tx Data Buffer and Command Register) ..................................... 728
28.2.8 SMB_SHCNT (SMB Standard Speed SCL High Count Register) .............................. 729
28.2.9 SMB_SLCNT (SMB Standard Speed SCL Low Count Register) ................................ 730
28.2.10 SMB_FHCNT (SMB Fast Speed SCL High Count Register) .................................. 730
28.2.11 SMB_FLCNT (SMB Fast Speed SCL Low Count Register) .................................... 731
28.2.12 SMB_HHCNT (SMB High Speed SCL High Count Register) .................................. 731
28.2.13 SMB_HLCNT (SMB High Speed SCL Low Count Register) ................................... 732
28.2.14 SMB_INTST (SMB Interrupt Status Register) ......................................................... 732
28.2.15 SMB_INTM (SMB Interrupt Mask Register) ............................................................ 734
28.2.16 SMB_RAW_INTR_STAT ......................................................................................... 735
28.2.17 SMB_RXTL (SMB Receive FIFO Threshold Register) ............................................ 737
28.2.18 SMB_TXTL (SMB Transmit FIFO Threshold Register) ........................................... 737
28.2.19 SMB_CINT (SMB Clear Combined and Individual Interrupt Register) .................... 737
CONTENTS
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X2000 IoT Application Processor Programming Manual
Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
28.2.20 SMB_CRXUF (SMB Clear RXUF Interrupt Register) .............................................. 738
28.2.21 SMB_CRXOF (SMB Clear RXOF Interrupt Register) .............................................. 738
28.2.22 SMB_CTXOF (SMB Clear TX_OVER Interrupt Register) ....................................... 739
28.2.23 SMB_CRXREQ (SMB Clear RDREQ Interrupt Register) ..................................... 739
28.2.24 SMB_CTXABT (SMB Clear TX_ABRT Interrupt Register) .................................... 739
28.2.25 SMB_CRXDN (SMB Clear RX_DONE Interrupt Register) ...................................... 740
28.2.26 SMB_CACT (SMB Clear ACTIVITY Interrupt Register) ........................................... 740
28.2.27 SMB_CSTP (SMB Clear STOP Interrupt Register) ................................................. 741
28.2.28 SMB_CSTT (SMB Clear START Interrupt Register) ................................................ 741
28.2.29 SMB_CGC (SMB Clear GEN_CALL Interrupt Register) .......................................... 741
28.2.30 SMB_ENABLE (SMB Enable Register) ................................................................... 742
28.2.31 SMB_ST(SMB Status Register) ............................................................................... 742
28.2.32 SMB_TXFLR(SMB Transmit FIFO Level Register) ................................................. 744
28.2.33 SMB_RXFLR(SMB Receive FIFO Level Register) .................................................. 744
28.2.34 SMB_SDAHD (SMB SDA Hold Time Register) ....................................................... 744
28.2.35 SMB_ABTSRC (SMB Transmit Abort Source Register ) ......................................... 745
28.2.36 SMB_SLV_DATA_NACK_ONLY (SMB Generate Slave Data NACK Register) ...... 747
28.2.37 SMB_DMACR (SMB DMA Control Register) ........................................................... 748
28.2.38 SMB_DMATDLR (SMB DMA Transmit Data Level Register) .................................. 749
28.2.39 SMB_DMARDLR (SMB DMA Transmit Data Level Register) .................................. 749
28.2.40 SMB_SDASU (SMB SDA Setup Register) .............................................................. 749
28.2.41 SMB_ACKGC (SMB ACK General Call Register) ................................................... 750
28.2.42 SMB_ENBST (SMB Enable Status) ......................................................................... 751
28.2.43 SMB_FS_SPKLEN (SMB SS and FS Spike Suppression Limit Register) .............. 752
28.2.44 SMB_HS_SPKLEN (SMB HS Spike Suppression Limit Register) .......................... 753
28.3 Operating Flow .................................................................................................................... 753
28.3.1 SMB Behavior .............................................................................................................. 753
28.3.2 Master Mode Operation ............................................................................................... 754
28.3.3 Configuration ................................................................................................................ 754
28.3.4 Dynamic SMBTAR or SMB10BITADDR_MASTER Update ......................................... 755
28.3.5 Master Transmit and Master Receive .......................................................................... 755
28.3.6 Slave Mode Operation ................................................................................................. 756
28.3.7 Initial Configuration ...................................................................................................... 756
28.3.8 Slave-Transmitter Operation for a Single Byte ............................................................ 756
28.3.9 Slave-Receiver Operation for a Single Byte ................................................................ 758
28.3.10 Slave-Transfer Operation For Bulk Transfers .......................................................... 758
28.3.11 Disabling SMB.......................................................................................................... 759
28.3.12 Procedure ................................................................................................................. 759
28.3.13 Summary the condition could flush TX FIFO ........................................................... 759
28.3.14 The condition could generate START, STOP and RESTART .................................. 760
29 Smart Card Controller .................................................................... 763
29.1 Overview .............................................................................................................................. 763
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