TAS5028: 8-Channel Digital Audio PWM Processor Manual

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TI-TAS5028是一款专用于数字音频处理的8通道数字音频PWM处理器，它在2004年发布，主要应用于DAV（Digital Audio/Speaker）系统中，提供详细的硬件规格、功能描述和技术手册。该文档详细介绍了TAS5028的关键特性与工作原理。 1. **系统架构**: - TAS5028系统包含音频输入/输出接口，用于处理模拟音频信号，并通过数字音频处理器(DAP)进行信号转换和处理。 - 数字音频处理部分采用I2C接口进行串行控制，允许用户配置和管理设备参数。 2. **功能特性**: - **音频输入/输出**：支持多通道音频输入和输出，可以连接到音频源和扬声器系统。 - **音频处理**：内置处理器负责信号的滤波、混音和格式转换，确保高质量的音频输出。 - **PWM处理**：采用脉宽调制技术，实现高效率的功率控制，同时具备直流阻断和去加重等高级功能。 3. **物理特性**: - 终端分配和描述详细说明了各接口的连接方式，便于硬件安装和接线。 - 订购信息可能包括封装类型、引脚布局等生产相关数据。 4. **电源与时钟**: - TAS5028需要外部电源供应，并利用PLL（锁相环路）稳定内部时钟，以确保音频信号的精确传输。 5. **控制接口**: - I2C接口是与外部微控制器或其他控制设备通信的主要方式，用于设置设备参数和获取状态信息。 6. **DAP架构**: - 文档深入探讨了DAP的工作原理和内部结构，包括可能的系数格式选择，有助于理解其内部信号处理流程。 7. **信号处理组件**: - 输入交叉条混频器负责混合不同通道的音频输入，而Bass和Treble控制允许用户调整低音和高音效果。 - 体积控制和自动/手动静音功能提供了音频增益和静音管理。 8. **输出组件**: - 输出混音器整合所有处理后的音频信号，准备发送到扬声器或外部设备。 9. **PWM功能详解**: - 高通滤波器和去加重功能有助于防止音频失真，并提高音频质量。 - AM干扰抑制可能是指对无线通信干扰的保护措施。 TI-TAS5028是一款高度集成的音频处理器，适合于音频系统设计者使用，提供了全面的技术支持和详细的操作指南。了解并掌握这些知识点对于有效应用这款产品以及优化音频系统的性能至关重要。

Introduction

SLES112 — June 2004 TAS5028

TERMINAL

DESCRIPTION

TERMIN-

ATION

5-V

TOLERANT

I/O

NO.

DESCRIPTION

TERMIN-

ATION

5-V

TOLERANT

I/O

NAME

28 SDIN4 DI 5 V Pulldown Serial audio data 4 input is one of the serial data input ports. SDIN4 supports four

discrete (stereo) data formats and is capable of inputting data at 64 Fs.

29 SDIN3 DI 5 V Pulldown Serial audio data 3 input is one of the serial data input ports. SDIN3 supports four

discrete (stereo) data formats and is capable of inputting data at 64 Fs.

30 SDIN2 DI 5 V Pulldown Serial audio data 2 input is one of the serial data input ports. SDIN2 supports four

discrete (stereo) data formats and is capable of inputting data at 64 Fs.

31 SDIN1 DI 5 V Pulldown Serial audio data 1 input is one of the serial data input ports. SDIN1 supports four

discrete (stereo) data formats and is capable of inputting data at 64 Fs.

32 RESERVED O

33 VR_DIG P Voltage reference for digital core supply 1.8 V. A pin-out of the internally regulated

1.8-V power used by digital core logic. A 0.47-µF low ESR capacitor should be

connected between this terminal and DVSS. This terminal must not be used to

power external devices

34 DVSS P Digital ground

35 DVSS P Digital ground

36 DVDD P 3.3-V digital power supply

37 BKND_ERR DI Pull up Active low. A backend error sequence is generated by applying logic low to this

terminal. The BKND_ERR

results in all system parameters unaffected, while all

H-bridge drive signals going to a hard mute (M) state.

38 DVSS P Digital ground

39 VALID DO Output indicating validity of PWM outputs active high

40 PWM_M_1 DO PWM 1 output (differential -)

41 PWM_P_1 DO PWM 1 output (differential +)

42 PWM_M_2 DO PWM 2 output (differential -)

43 PWM_P_2 DO PWM 2 output (differential +)

44 PWM_M_3 DO PWM 3 output (differential -)

45 PWM_P_3 DO PWM 3 output (differential +)

46 PWM_M_4 DO PWM 4 output (differential -)

47 PWM_P_4 DO PWM 4 output (differential +)

48 VR_PWM P Voltage reference for digital PWM core supply 1.8 V. A pin-out of the internally

regulated 1.8-V power used by digital PWM core logic. A 0.1-µF low ESR capacitor

should be connected between this terminal and DVSS_PWM. This terminal must

not be used to power external devices.

49 PWM_M_7 DO PWM 7 (Line out L) output (differential -)

50 PWM_P_7 DO PWM 7 (Line out L) output (differential +)

51 PWM_M_8 DO PWM 8 (Line out R) output (differential -)

52 PWM_P_8 DO PWM 8 (Line out R) output (differential +)

53 DVSS_PWM P Digital ground for PWM

54 DVDD_PWM P 3.3-V digital power supply for PWM

55 PWM_M_5 DO PWM 5 output (differential -)

56 PWM_P_5 DO PWM 5 output (differential +)

57 PWM_M_6 DO PWM 6 output (differential -)

58 PWM_P_6 DO PWM 6 output (differential +)

59 PWM_HPML DO PWM left channel headphone (differential -)

60 PWM_HPPL DO PWM left channel headphone (differential +)

61 PWM_HPMR DO PWM right channel headphone (differential -)

62 PWM_HPPR DO PWM right channel headphone (differential +)

Introduction

SLES112 — June 2004TAS5028

TERMINAL

DESCRIPTION

TERMIN-

ATION

5-V

TOLERANT

I/O

NO.

DESCRIPTION

TERMIN-

ATION

5-V

TOLERANT

I/O

NAME

63 MCLK DI 5 V Pulldown MCLK is a 3.3-V clock master clock input. The input frequency of this clock can

range from 4 MHz to 50 MHz.

64 RESERVED Connect to digital ground

NOTES: 1. Type: A = analog; D = 3.3-V digital; P = power / ground / decoupling; I = input; O = output

2. All pullups are 200-µA weak pullups and all pulldowns are 200-µA weak pull downs. The pullups and pulldowns are included to assure

proper input logic levels if the terminals are left unconnected (pullups => logic 1 input; pulldowns => logic 0 input). Devices that drive

inputs with pull ups must be able to sink 200 µA, while maintaining a logic 0 drive level. Devices that drive inputs with pulldowns must

be able to source 200 µA, while maintaining a logic ‘1’ drive level.

3. If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling

capacitors of equal value provide an extended high frequency supply decoupling. This approach avoids the potential of producing

parallel resonance circuits that have been observed when paralleling capacitors of different values.

4. 13.5-MHz crystal (HCM49)

1.4 TAS5028 Functional Description

Figure 1-4 shows the TAS5028 functional structure. The next sections describe the TAS5028 functional

blocks:

• Power Supply

• Clock, PLL, and Serial Data Interface

• Serial Control Interface

• Device Control

• Digital Audio Processor (DAP)

• Pulse Width Modulation (PWM) Processor

1.4.1 Power Supply

The power supply section contains supply regulators that provide analog and digital regulated power for

various sections of the TAS5028. The analog supply supports the analog PLL, while digital supplies support

the digital PLL, the digital audio processor (DAP), the pulse width modulator (PWM), and the output control

(reclocker). The regulators can also be turned off when terminals RESET

and PDN are both low.

1.4.2 Clock, PLL, and Serial Data Interface

The TAS5028 is a clock slave only device and it requires the use of an external 13.5 MHz crystal. It accepts

MCLK, SCLK, and LRCLK as inputs only.

The TAS5028 uses the external crystal to provide a time base for:

• Continuous data and clock error detection and management

• Automatic data rate detection and configuration

• Automatic MCLK rate detection and configuration (automatic bank switching)

• Supporting I

C operation/ communication while MCLK is absent

The TAS5028 automatically handles clock errors, data rate changes, and master clock frequency changes

without requiring intervention from an external system controller. This feature significantly reduces system

complexity and design.

Introduction

SLES112 — June 2004 TAS5028

1.4.2.1 Serial Audio Interface

The TAS5028 operates as a slave only / receive only serial data interface in all modes. The TAS5028 has four

PCM serial data interfaces to permit eight channels of digital data to be received though the SDIN1, SDIN2,

SDIN3, and SDIN4 inputs. The serial audio data is in MSB first, two’s complement format.

The serial data input interface of the TAS5028 can be configured in right justified, I

S, or left-justified modes.

The serial data interface format is specified using the I

C data interface control register. The supported formats

and word lengths are shown in Table 1-1.

Table 1-1. Serial Data Formats

RECEIVE SERIAL DATA

INTERFACE FORMAT

WORD LENGTHS

Right justified 16

Right justified 20

Right justified 24

I2S 16

I2S 20

I2S 24

Left Justified 16

Left Justified 20

Left Justified 24

Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5028 accepts 32-, 38-, 44.1-, 48-, 88.2-,

96-, 176.4-, and 192-kHz serial data in 16-, 20-, or 24-bit data in left, right, and I

S serial data formats using

a 64-Fs SCLK clock and a 128, 192, 256, 384, 512, or 768 x Fs MCLK rates (up to a maximum of 50 MHz).

The parameters of this clock and serial data interface are I

C configurable.

1.4.3 I

C Serial Control Interface

The TAS5028 has an I

C serial control slave interface (address 0x36) to receive commands from a system

controller. The serial control interface supports both normal-speed (100 kHz) and high-speed (400 kHz)

operations without wait states. Since the TAS5028 has a crystal time base, this interface operates even when

MCLK is absent.

The serial control interface supports both single byte and multi-byte read / write operations for status registers

and the general control registers associated with the PWM. However, for the DAP data processing registers,

the serial control interface also supports multiple byte (4 byte) write operations.

The I

C supports a special mode which permits I

C write operations to be broken up into multiple data write

operations that are multiples of 4 data bytes. These are 6 byte, 10 byte, 14 byte, 18 byte ... etc write operations

that are composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes of data.

This permits the system to incrementally write large register values without blocking other I

C transactions.

In order to use this feature, the first chunk of data is written to the target I

C address and each chunk of

subsequent data is written to a special append register (0xFE), until all the data is written and a stop bit is sent.

An incremental read operation is not supported.

1.4.4 Device Control

The TAS5028 control section provides the control and sequencing for the TAS5028. The device control

provides both high and low level control for the serial control interface, clock and serial data interfaces, digital

audio processor, and pulse width modulator sections.

1.4.5 Digital Audio Processor (DAP)

The DAP arithmetic unit is used to implement all audio processing functions – soft volume, bass and treble

processing, and input and output mixing. Figure 1-6 shows the TAS5028 DAP architecture.

Introduction

SLES112 — June 2004TAS5028

The DAP accepts 24-bit data signal from the serial data interface and outputs 32-bit data to the PWM section.

The DAP supports two configurations, one for 32-kHz – 96-kHz data and one for 176.4-kHz to 192-kHz data.

1.4.5.1 TAS5028 Audio Processing Configurations

The 32 - 96 kHz configuration supports eight channels of data processing that can be configured as eight

channels or six channels with two channels for separate stereo line outputs.

The 176.4 - 192 kHz configuration supports three channels of signal processing with five channels passed

though (or derived from the three processed channels).

To efficiently support the processing requirements of both multi-channel 32 – 96-kHz data and the two channel

176.4 and 192-kHz data, the TAS5028 supports separate audio processing features for 32 –96-kHz data rates

and for 176.4 and 192 kHz. See Table 2 for a summary of TAS5028 processing feature sets.

1.4.5.2 TAS5028 Audio Signal Processing Functions

The DAP provides 7 primary signal processing functions.

1. The data processing input has a full 8x8 input crossbar mixer. This enables each input to be any ratio of

the eight input channels.

2. Two I

C programmable threshold detectors in each channel support auto mute.

3. Four soft bass and treble tone controls with ±18 dB range, programmable corner frequencies, and 2nd

order slopes. In 8-channel mode, bass and treble controls are normally configured as follows:

- Bass and Treble 1: Channel 1 (Left), Channel 2 (Right), and Channel 7 (Center)

- Bass and Treble 2: Channel 3 (Left Surround) and Channel 4 (Right Surround)

- Bass and Treble 3: Channel 5 (Left Back Surround) and Channel 6 (Right Back Surround)

- Bass and Treble 4: Channel 8 (Subwoofer)

4. Individual channel and master volume controls. Each control provides an adjustment range of +18 dB to

–127 dB. This permits a total volume device control range of +36 dB to –127 dB plus mute. The master

volume control can be configured to control six or eight channels. The DAP soft volume and mute update

interval is I

C programmable. The update is performed at a fixed rate regardless of the sample rate.

5. 8x2 output mixer (channels 1-6). Each output can be any ratio of any two signal processed channels.

6. 8x3 output mixer (channels 7 and 8). Each output can be any ratio of any three signal processed channels.

7. The DAP maintains three sets of coefficient banks that are used to maintain separate sets of sample rate

dependent parameters for the tone controls in RAM. These can be set to be automatically selected for

one or more data sample rates or can be manually selected under I

C program control. This feature

enables coefficients for different sample rates to be stored in the TAS5028 and then select when needed.

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TAS5028: 8-Channel Digital Audio PWM Processor Manual

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