WP446 (v1.0.1) April 18, 2014 www.xilinx.com 1
© Copyright 2014 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the
United States and other countries. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the EU and other countries. All
other trademarks are the property of their respective owners.
The JESD204B standard offers key advantages over
LVDS, including higher bandwidth, fewer device
pins, reduced board area, and lower power. For these
reasons, it is expected to be quickly adopted for
wireless, medical, SDR, and radar applications that
require high bandwidth, a large number of channels,
or robust, easy-to-use configurability.
Complete solutions are available from Xilinx and its
ecosystem partners that allow users to quickly bring
up JESD204B systems using standard Xilinx
development boards and software tools. The
Vivado® Interactive Logic Analyzer leverages
dedicated silicon hardware in each transceiver to
generate 2D Eye Scans and BER results in real time.
This 2D Eye Scan logic not only simplifies board
debug but enables constant BER calculations to
monitor the integrity of the link once deployed to the
field. It is a unique capability that enables
pre-emptive link degradation and failure capability
to any system using Xilinx devices.
White Paper: All Programmable FPGAs and SoCs
WP446 (v1.0.1) April 18, 2014
Comprehensive JESD204B Solution
Accelerates and Simplifies Development
By: Tom Hill