没有合适的资源?快使用搜索试试~ 我知道了~
首页CEVA-XC4000 TM MSS Vol-III FIC总线协议详解
CEVA-XC4000 TM MSS Vol-III FIC总线协议详解
需积分: 50 17 下载量 83 浏览量
更新于2024-07-19
1
收藏 2.18MB PDF 举报
本文档是关于CEVA-XC4000 TM 架构的详细规格,特别是Memory Subsystem (MSS)部分,适用于Vol-III版本,修订版为1.2.0,发布日期为2012年12月。CEVA是一家专注于数字信号处理(DSP)技术的公司,提供的资料可能受到法律保护,未经许可的复制是被禁止的。 FIC总线(Fast Input/Output Controller)在文中占据了核心地位,它是一种高效的数据传输接口,用于连接CEVA4000处理器中的各个模块,如内存、外设以及内部逻辑。FIC总线的设计旨在优化系统性能,确保数据在处理器内部和外部组件之间的快速交换,这对于实时处理和多媒体应用至关重要。 文档详细描述了FIC总线的工作原理、架构特性以及它如何支持CEVA4000系列的内存管理。这包括地址映射、数据宽度、时钟同步机制、错误检测与校正等关键要素。FIC总线协议可能包含仲裁、中断管理、数据缓存和一致性控制等方面的规定,以确保系统的可靠性和一致性。 此外,文档还强调了版权声明和免责声明,说明所有信息可能随时更新,且不构成对CEVA公司的承诺。用户在使用这些信息时必须承担风险,CEVA及其子公司不对材料中的错误或遗漏承担责任,并且不承担因使用该材料产生的特殊、直接、间接或后果性损失。 阅读这份手册对于理解CEVA4000系列产品的内存子系统工作方式以及如何正确配置和利用FIC总线,对系统设计师、开发者和工程师来说具有重要意义。它提供了一个深入的技术参考,有助于提升系统性能和整体设计质量。
资源详情
资源推荐
![](https://csdnimg.cn/release/download_crawler_static/10342407/bg10.jpg)
CEVA-XC4000 Architecture
Specification Vol III
DSP Division
Rev 1.2.0 December 2012
Confidential and Proprietary · Unauthorized Reproduction Prohibited
Copyright © 2012 – CEVA
®
, Inc.
xiv
Table 1-77: PSVM LO Register Description ............................................................................................................ 1-184
Table 1-78: DBC Register Description ..................................................................................................................... 1-186
Table 1-79: PGR Register Description ..................................................................................................................... 1-187
Table 1-80: STRET Bit/Field Description ................................................................................................................ 1-187
Table 1-81: SPRET Bit/Field Description ................................................................................................................ 1-188
Table 1-82: STSD Bit/Field Description .................................................................................................................. 1-188
Table 1-83: SPSD Bit/Field Description .................................................................................................................. 1-188
Table 1-84: LRUA Slot configuration Register (low part) Description.................................................................... 1-190
Table 1-85: LRUA Slot Configuration Register (high part) Description.................................................................. 1-193
Table 1-86: LRUA slot priority region register Description ..................................................................................... 1-194
Table 1-87: LRUA Weight Register (low part) Description ..................................................................................... 1-194
Table 1-88: LRUA Weight Register (high part) Description ................................................................................... 1-195
Table 1-89: Common Register Description .............................................................................................................. 1-197
Table 1-90: COM_STS Register Description ........................................................................................................... 1-197
Table 1-91: COM_INT_EN Register Description .................................................................................................... 1-197
Table 1-92: Start Address Register Description ....................................................................................................... 1-198
Table 1-93: Top Address Register Description ........................................................................................................ 1-198
Table 1-94: SNOOP_CSR Register Description ...................................................................................................... 1-199
Table 1-95: FIC Slave Configuration Register Description ...................................................................................... 1-201
Table 1-96: FICMR Configuration Register Description ......................................................................................... 1-203
Table 1-97: ADD0_START Configuration Register Description ............................................................................ 1-204
Table 1-98: ADD1_START Configuration Register Description ............................................................................ 1-204
Table 1-99: ADD2_START Configuration Register Description ............................................................................ 1-205
Table 1-100: ADD3_START Configuration Register Description .......................................................................... 1-205
Table 1-101: ADD4_START Configuration Register Description .......................................................................... 1-206
Table 1-102: ADD5_START Configuration Register Description .......................................................................... 1-206
Table 1-103: ADD6_START Configuration Register Description .......................................................................... 1-207
Table 1-104: ADD7_START Configuration Register Description .......................................................................... 1-207
Table 1-105: Queue External Pointer Descriptor Push Register Description ........................................................... 1-209
Table 1-106: Queue Internal Pointer Descriptor Push Register Description ............................................................ 1-209
Table 1-107: Queue Transfer Control Descriptor Push Register Description .......................................................... 1-210
Table 1-108: Queue Priority and Frame Location Descriptor Push Register Description ........................................ 1-210
Table 1-109: Queue Push Number Register Description .......................................................................................... 1-211
Table 1-110: Buffer Manager Interrupt Configuration Register Description ........................................................... 1-213
Table 1-111: Buffer Manager Read or Write Pointer Interrupt Address Register Description ................................. 1-214
Table 1-112: Buffer Manager Underflow Interrupt Packet Size Register Description ............................................. 1-214
Table 1-113: Queue Manager Violation Indication Mask Register Description....................................................... 1-215
Table 1-114: QMAN and BMAN interrupt status Register Description .................................................................. 1-216
Table 1-115: Queue Manager Reset Register Description ........................................................................................ 1-217
![](https://csdnimg.cn/release/download_crawler_static/10342407/bg11.jpg)
DSP Division
Rev 1.2.0 December 2012
List of Tables
Confidential and Proprietary · Unauthorized Reproduction Prohibited
Copyright © 2012 – CEVA
®
, Inc.
xv
Table 1-116: Buffer Manager Reset Register Description ....................................................................................... 1-218
Table 1-117: Queue Manager Active Register Description ...................................................................................... 1-219
Table 1-118: Queue X Enable and Depth Register Description ............................................................................... 1-222
Table 1-119: Queue X first address Register Description ........................................................................................ 1-223
Table 1-120: Queue X Base Pointer Register Description ....................................................................................... 1-223
Table 1-121: Queue X Chunk Size Register Description ......................................................................................... 1-224
Table 1-122: Queue X Descriptor Enable Incrementer Register Description........................................................... 1-224
Table 1-123: Queue X Enabled Descriptors Counter Register Description ............................................................. 1-225
Table 1-124: Queue X Internal Read Pointer Register Description .......................................................................... 1-226
Table 1-125: Queue X External Pointer Descriptor Register Description ................................................................ 1-226
Table 1-126: Queue X Internal Pointer Descriptor Register Description ................................................................. 1-227
Table 1-127: Queue X Transfer Control Descriptor Register Description ............................................................... 1-227
Table 1-128: Queue X Frame Length Descriptor Register Description ................................................................... 1-228
Table 1-129: Buffer X start address Register Description ........................................................................................ 1-230
Table 1-130: Buffer X Size Register Description ..................................................................................................... 1-230
Table 1-131: Buffer X Pointer Increment Control Register Description .................................................................. 1-231
Table 1-132: Buffer X Pointer Increment Register Description ............................................................................... 1-232
Table 1-133: Buffer X Full/Empty Control Register Description ............................................................................ 1-233
Table 1-134: Buffer X Write Pointer Register Description ...................................................................................... 1-234
Table 1-135: Buffer X Read Pointer Register Description ....................................................................................... 1-234
Table 1-136: Buffer X Expected Write Pointer Register Description ...................................................................... 1-235
Table 1-137: Buffer X Expected Read Pointer Register Description ....................................................................... 1-235
Table 1-138: Buffer X Sniffer Output Accumulator Register Description ............................................................... 1-236
Table 2-1: External Device Access Port Input Signals ................................................................................................. 2-2
Table 2-2: External Device Access Port Output ........................................................................................................... 2-3
Table 2-3: AXI Master Port Output Signals ................................................................................................................. 2-9
Table 2-4: AXI Master Port Input Signal ................................................................................................................... 2-11
Table 2-5: FICSR Port Input Signals .......................................................................................................................... 2-15
Table 2-6: FICSR Port Output Signals ....................................................................................................................... 2-15
Table 2-7: FICSW Port Input Signals ......................................................................................................................... 2-17
Table 2-8: FICSW Port Output Signals ...................................................................................................................... 2-17
Table 2-9: FICMR Port Output Signals ...................................................................................................................... 2-20
Table 2-10: FICMR Port Input Signal ........................................................................................................................ 2-20
Table 2-11: FICMW Port Output Signals ................................................................................................................... 2-21
Table 2-12: FICMW port Input Signal ....................................................................................................................... 2-21
Table 2-13: I/O Port Output Signals ........................................................................................................................... 2-22
Table 2-14: I/O Port Input Signals ............................................................................................................................. 2-22
Table 2-15: JTAG Output Signals .............................................................................................................................. 2-27
Table 2-16: JTAG Input Signals ................................................................................................................................. 2-27
![](https://csdnimg.cn/release/download_crawler_static/10342407/bg12.jpg)
CEVA-XC4000 Architecture
Specification Vol III
DSP Division
Rev 1.2.0 December 2012
Confidential and Proprietary · Unauthorized Reproduction Prohibited
Copyright © 2012 – CEVA
®
, Inc.
xvi
Table 2-17: PSU Output Signals ................................................................................................................................. 2-27
Table 2-18: PSU Input Signals ................................................................................................................................... 2-28
Table 2-19: General Output Signals ........................................................................................................................... 2-29
Table 2-20: General Input Signals .............................................................................................................................. 2-29
Table 2-21: QMAN Output Signals ............................................................................................................................ 2-30
Table 2-22: QMAN Input Signals .............................................................................................................................. 2-31
Table 2-23: BMAN Output Signals ............................................................................................................................ 2-34
Table 2-24: BMAN Input Signals ............................................................................................................................... 2-37
![](https://csdnimg.cn/release/download_crawler_static/10342407/bg13.jpg)
DSP Division
Rev 1.2.0 December 2012
List of Examples
Confidential and Proprietary · Unauthorized Reproduction Prohibited
Copyright © 2012 – CEVA
®
, Inc.
xvii
List of Examples
Example 1-1: DMA Cache Preload ............................................................................................................................ 1-18
Example 1-2: Write Buffer Data Flow – Writes Originated in the CEVA-X and VCU ............................................. 1-35
Example 1-3: AXI Exclusive Access to Shared Memory Peripheral ......................................................................... 1-64
Example 1-4: Consecutive I/O Transfers ................................................................................................................. 1-119
Example 1-5: Changing from Free Run to DPS Routine .......................................................................................... 1-125
Example 1-6: Changing DPS to Free Run Routine .................................................................................................. 1-126
Example 1-7: Light Sleep Entry Routine .................................................................................................................. 1-127
Example 1-8: Standby Entry Routine ....................................................................................................................... 1-130
Example 1-9: Retention Entering Routine ................................................................................................................ 1-137
Example 1-10: Shutdown Entry Routine .................................................................................................................. 1-139
Example 1-11: Shutdown Entry Routine .................................................................................................................. 1-141
Example 1-12: Reading an Internal Register ............................................................................................................ 1-151
Example 1-13: Writing a Whole Accumulator ......................................................................................................... 1-152
Example 1-14: Writing to the Output Vector ........................................................................................................... 1-152
![](https://csdnimg.cn/release/download_crawler_static/10342407/bg14.jpg)
剩余297页未读,继续阅读
![pdf](https://img-home.csdnimg.cn/images/20210720083512.png)
![pdf](https://img-home.csdnimg.cn/images/20210720083512.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![pdf](https://img-home.csdnimg.cn/images/20210720083512.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![doc](https://img-home.csdnimg.cn/images/20210720083327.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![docx](https://img-home.csdnimg.cn/images/20210720083331.png)
![docx](https://img-home.csdnimg.cn/images/20210720083331.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![](https://profile-avatar.csdnimg.cn/ce13ec214a3c49048f868194ba083a40_htgoco.jpg!1)
马車
- 粉丝: 116
- 资源: 7
上传资源 快速赚钱
我的内容管理 展开
我的资源 快来上传第一个资源
我的收益
登录查看自己的收益我的积分 登录查看自己的积分
我的C币 登录后查看C币余额
我的收藏
我的下载
下载帮助
![](https://csdnimg.cn/release/wenkucmsfe/public/img/voice.245cc511.png)
最新资源
- 多模态联合稀疏表示在视频目标跟踪中的应用
- Kubernetes资源管控与Gardener开源软件实践解析
- MPI集群监控与负载平衡策略
- 自动化PHP安全漏洞检测:静态代码分析与数据流方法
- 青苔数据CEO程永:技术生态与阿里云开放创新
- 制造业转型: HyperX引领企业上云策略
- 赵维五分享:航空工业电子采购上云实战与运维策略
- 单片机控制的LED点阵显示屏设计及其实现
- 驻云科技李俊涛:AI驱动的云上服务新趋势与挑战
- 6LoWPAN物联网边界路由器:设计与实现
- 猩便利工程师仲小玉:Terraform云资源管理最佳实践与团队协作
- 类差分度改进的互信息特征选择提升文本分类性能
- VERITAS与阿里云合作的混合云转型与数据保护方案
- 云制造中的生产线仿真模型设计与虚拟化研究
- 汪洋在PostgresChina2018分享:高可用 PostgreSQL 工具与架构设计
- 2018 PostgresChina大会:阿里云时空引擎Ganos在PostgreSQL中的创新应用与多模型存储
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
![](https://img-home.csdnimg.cn/images/20220527035711.png)
![](https://img-home.csdnimg.cn/images/20220527035711.png)
![](https://img-home.csdnimg.cn/images/20220527035111.png)
安全验证
文档复制为VIP权益,开通VIP直接复制
![](https://csdnimg.cn/release/wenkucmsfe/public/img/green-success.6a4acb44.png)