CEVA-XC4000 TM MSS Vol-III FIC总线协议详解
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本文档是关于CEVA-XC4000 TM 架构的详细规格，特别是Memory Subsystem (MSS)部分，适用于Vol-III版本，修订版为1.2.0，发布日期为2012年12月。CEVA是一家专注于数字信号处理(DSP)技术的公司，提供的资料可能受到法律保护，未经许可的复制是被禁止的。
FIC总线（Fast Input/Output Controller）在文中占据了核心地位，它是一种高效的数据传输接口，用于连接CEVA4000处理器中的各个模块，如内存、外设以及内部逻辑。FIC总线的设计旨在优化系统性能，确保数据在处理器内部和外部组件之间的快速交换，这对于实时处理和多媒体应用至关重要。
文档详细描述了FIC总线的工作原理、架构特性以及它如何支持CEVA4000系列的内存管理。这包括地址映射、数据宽度、时钟同步机制、错误检测与校正等关键要素。FIC总线协议可能包含仲裁、中断管理、数据缓存和一致性控制等方面的规定，以确保系统的可靠性和一致性。
此外，文档还强调了版权声明和免责声明，说明所有信息可能随时更新，且不构成对CEVA公司的承诺。用户在使用这些信息时必须承担风险，CEVA及其子公司不对材料中的错误或遗漏承担责任，并且不承担因使用该材料产生的特殊、直接、间接或后果性损失。
阅读这份手册对于理解CEVA4000系列产品的内存子系统工作方式以及如何正确配置和利用FIC总线，对系统设计师、开发者和工程师来说具有重要意义。它提供了一个深入的技术参考，有助于提升系统性能和整体设计质量。
CEVA-XC4000 Architecture
Specification Vol III
DSP Division
Rev 1.2.0 December 2012
Confidential and Proprietary · Unauthorized Reproduction Prohibited
Copyright © 2012 – CEVA
®
, Inc.
xiv
Table 1-77: PSVM LO Register Description ............................................................................................................ 1-184
Table 1-78: DBC Register Description ..................................................................................................................... 1-186
Table 1-79: PGR Register Description ..................................................................................................................... 1-187
Table 1-80: STRET Bit/Field Description ................................................................................................................ 1-187
Table 1-81: SPRET Bit/Field Description ................................................................................................................ 1-188
Table 1-82: STSD Bit/Field Description .................................................................................................................. 1-188
Table 1-83: SPSD Bit/Field Description .................................................................................................................. 1-188
Table 1-84: LRUA Slot configuration Register (low part) Description.................................................................... 1-190
Table 1-85: LRUA Slot Configuration Register (high part) Description.................................................................. 1-193
Table 1-86: LRUA slot priority region register Description ..................................................................................... 1-194
Table 1-87: LRUA Weight Register (low part) Description ..................................................................................... 1-194
Table 1-88: LRUA Weight Register (high part) Description ................................................................................... 1-195
Table 1-89: Common Register Description .............................................................................................................. 1-197
Table 1-90: COM_STS Register Description ........................................................................................................... 1-197
Table 1-91: COM_INT_EN Register Description .................................................................................................... 1-197
Table 1-92: Start Address Register Description ....................................................................................................... 1-198
Table 1-93: Top Address Register Description ........................................................................................................ 1-198
Table 1-94: SNOOP_CSR Register Description ...................................................................................................... 1-199
Table 1-95: FIC Slave Configuration Register Description ...................................................................................... 1-201
Table 1-96: FICMR Configuration Register Description ......................................................................................... 1-203
Table 1-97: ADD0_START Configuration Register Description ............................................................................ 1-204
Table 1-98: ADD1_START Configuration Register Description ............................................................................ 1-204
Table 1-99: ADD2_START Configuration Register Description ............................................................................ 1-205
Table 1-100: ADD3_START Configuration Register Description .......................................................................... 1-205
Table 1-101: ADD4_START Configuration Register Description .......................................................................... 1-206
Table 1-102: ADD5_START Configuration Register Description .......................................................................... 1-206
Table 1-103: ADD6_START Configuration Register Description .......................................................................... 1-207
Table 1-104: ADD7_START Configuration Register Description .......................................................................... 1-207
Table 1-105: Queue External Pointer Descriptor Push Register Description ........................................................... 1-209
Table 1-106: Queue Internal Pointer Descriptor Push Register Description ............................................................ 1-209
Table 1-107: Queue Transfer Control Descriptor Push Register Description .......................................................... 1-210
Table 1-108: Queue Priority and Frame Location Descriptor Push Register Description ........................................ 1-210
Table 1-109: Queue Push Number Register Description .......................................................................................... 1-211
Table 1-110: Buffer Manager Interrupt Configuration Register Description ........................................................... 1-213
Table 1-111: Buffer Manager Read or Write Pointer Interrupt Address Register Description ................................. 1-214
Table 1-112: Buffer Manager Underflow Interrupt Packet Size Register Description ............................................. 1-214
Table 1-113: Queue Manager Violation Indication Mask Register Description....................................................... 1-215
Table 1-114: QMAN and BMAN interrupt status Register Description .................................................................. 1-216
Table 1-115: Queue Manager Reset Register Description ........................................................................................ 1-217
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