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首页"数字验证覆盖率收集用户手册-技术覆盖范围及使用指南，版本D-2010.06"

"数字验证覆盖率收集用户手册-技术覆盖范围及使用指南，版本D-2010.06"

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The Coverage Technology User Guide, Version D-2010.06, published in June 2010, provides comprehensive information on the collection of coverage data for numerical verification. This user manual is created by Synopsys, Inc. and is subject to copyright and proprietary information laws. The manual offers detailed instructions on how to use the coverage technology to collect and analyze numerical verification data. It covers topics such as the importance of coverage data, how to set up and configure the coverage tool, and how to interpret and utilize the collected data effectively. Users are encouraged to provide feedback on the manual by emailing their comments to vcs_support@synopsys.com. This allows for continuous improvement and updates to the user guide based on user input and suggestions. Overall, the Coverage Technology User Guide serves as a valuable resource for users looking to enhance their numerical verification processes. It is an essential tool for anyone working with coverage data in the field of verification and validation. With its clear and concise instructions, users can confidently navigate the process of collecting and analyzing coverage data to ensure the accuracy and reliability of their numerical verification results.

1-4

Unified Coverage Reporting

Coverage Flow

Following is a high level picture of the VCS Coverage flow:

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Unified Coverage Reporting

This document is created based on this flow.

Types of Coverage

This section provides introductory descriptions of the following types

of coverage metrics.

• “Line Coverage”

• “Toggle Coverage”

• “Condition Coverage”

• “FSM Coverage”

• “Branch Coverage”

• “Functional Coverage”

Line Coverage

Line coverage (or statement coverage) shows you which lines of

code are exercised — and which ones are not — by your testbench

during a simulation run. VCS generates metrics for total coverage of

lines, blocks, and branches that tell you how much of your code is

actually executed by the tests. Line coverage is applied to signal and

variable assignments in HDL code and gives an indication of the

number of times each assignment statement was executed when the

design was simulated. A zero execution count pin-points a line of

code that has not been exercised that could be the source of a

potential design error.

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Unified Coverage Reporting

Line coverage also produces annotated listings, which identify the

unexercised statements, therefore, giving you the information you

need to write more tests to complete the coverage. However,

coverage reports do not tell you how many times a line of code is

executed.

In line coverage, VCS keeps track of the following in the source

code:

• Individual procedural statements

• Procedural statement blocks

• Procedural statement block type

• Missing (implied) conditional statements

Note:

• Statement blocks consist of a set of individual procedural

statements executed sequentially and always executed together

in the same time step.

• By default, line coverage does not keep track of continuous

assignment statements, but you can enable it; see

“Enabling Line

Coverage for Continuous Assignments” .

Line Coverage for Verilog

VCS tracks the following types of Verilog procedural statements:

• Statements that cause a simulation event, such as a procedural

assignment statement, or a system task.

• Statements that control which other statements are executed,

such as a while or an if statements.

The following code example illustrates what is covered in Verilog:

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Unified Coverage Reporting

Example 1-1 Monitored Statements in Line Coverage

module top;

reg clk;

reg [8:0] data;

wire [8:0] results;

initial

begin

$display("Assigning initial values");

clk=0; data=256;

#100 $finish;

end

always

#3 clk=~clk;

dev dev1 (results,clk,data);

endmodule

module dev (out,clock,in);

output [8:0] out;

input clock;

input [8:0] in;

reg [8:0] out;

reg en;

task splitter;

input [8:0] tin;

output [8:0] tout;

begin

tout = tin/2;

end

endtask

always @ (posedge clock)

begin

if (in % 2 !== 0)

$display("error cond, input not even");

else

out = in;

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Unified Coverage Reporting

if (in % 2 == 0)

en =

while (en)

forever

case (out % 2)

!0 : #0 $finish;

0 : #5 splitter(out,out);

endcase

end

endmodule

In Example 1-1, the boldface lines contain statements that VCS

tracks for line coverage.

VCS line coverage also includes information about always and initial

blocks and other types of blocks of code. In line coverage, a block is

a nesting level in the code, not so much a level in the hierarchy, but

a level of control of the execution of the procedural code. Typically,

you change the indentation of your source code for a nesting level.

Example 1-2 illustrates the code blocks in the source code in

Example 1-1. It is interrupted in a number of places to explain the

blocks.

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