![](https://csdnimg.cn/release/download_crawler_static/13082619/bg12.jpg)
42.3.1 Brief Description of the Sub-Block ................................................................................................ 42-4
42.3.2 Data Flow ...................................................................................................................................... 42-5
42.3.3 Overview of the Color Data .......................................................................................................... 42-8
42.3.4 Color Space Conversion ............................................................................................................. 42-23
42.3.5 Palette Usage ............................................................................................................................. 42-25
42.3.6 Window Blending ........................................................................................................................ 42-28
42.3.7 Image Enhancement .................................................................................................................. 42-37
42.3.8 VTIME Controller Operation ....................................................................................................... 42-44
42.3.9 Setting of Commands ................................................................................................................. 42-47
42.3.10 Virtual Display ........................................................................................................................... 42-50
42.3.11 RGB Interface Specification ..................................................................................................... 42-51
42.3.12 LCD Indirect i80 System Interface ............................................................................................ 42-60
42.4 I/O Description ................................................................................................................................... 42-64
42.5 Register Description ........................................................................................................................... 42-65
42.5.1 Register Map Summary .............................................................................................................. 42-66
42.5.2 Palette Memory ........................................................................................................................... 42-72
42.5.3 Control Register .......................................................................................................................... 42-73
42.5.4 Gamma Lookup Table .............................................................................................................. 42-145
42.5.5 Shadow Windows Control ........................................................................................................ 42-146
42.5.6 Palette Ram .............................................................................................................................. 42-147
43 CAMERA INTERFACE AND SCALER ...................................................... 43-1
43.1 Overview .............................................................................................................................................. 43-1
43.2 Features of CAMIF ............................................................................................................................... 43-3
43.3 External Interface ................................................................................................................................. 43-5
43.4 Timing Diagram and Data Alignment of Camera ................................................................................. 43-6
43.4.1 Timing Diagram of ITU Camera .................................................................................................... 43-6
43.4.2 MIPI CSI Data Alignment from MIPI Camera ............................................................................. 43-10
43.5 External Connection Guide ................................................................................................................ 43-11
43.6 Camera Interface Operation .............................................................................................................. 43-12
43.6.1 Input/Output DMA Ports ............................................................................................................. 43-12
43.6.2 Clock Domain ............................................................................................................................. 43-13
43.6.3 Frame Memory Hierarchy ........................................................................................................... 43-14
43.6.4 Memory Storing Method ............................................................................................................. 43-15
43.6.5 Timing Diagram for Register Setting .......................................................................................... 43-16
43.6.6 Timing Diagram for last IRQ ....................................................................................................... 43-18
43.6.7 Timing Diagram for IRQ (Memory Data Scaling Mode).............................................................. 43-20
43.6.8 Input DMA Feature ..................................................................................................................... 43-21
43.6.9 Camera Interlace Input Support ................................................................................................. 43-22
43.7 Input/Output Description .................................................................................................................... 43-23
43.8 Register Description ........................................................................................................................... 43-24
43.8.1 Register Map Summary .............................................................................................................. 43-24
44 FIMC_LITE (CAMERA INTERFACE) ........................................................ 44-1
44.1 Overview of Camera Interface in FIMC_LITE ...................................................................................... 44-1
44.1.1 Block Diagram .............................................................................................................................. 44-1
44.2 Timing Diagram and Data Alignment of Camera ................................................................................. 44-2
44.2.1 Parallel INTERFACE .................................................................................................................... 44-2
44.2.2 MIPI CSI Slave Interface .............................................................................................................. 44-3
44.2.3 Local Output Interface Data Alignment ........................................................................................ 44-4
44.3 External Connection Guide .................................................................................................................. 44-5
44.4 Input / Output Path ............................................................................................................................... 44-6