MPC5553/MPC5554 微控制器参考手册详解

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"MPC5553_4 Reference_manual - MPC5553 and MPC5554 Microcontroller Reference Manual, Rev. 3.1 from 11/2005." 本文档是Freescale Semiconductor（现为NXP Semiconductors的一部分）发布的MPC5553和MPC5554微控制器的参考手册，版本3.1，发布于2005年11月。MPC5553和MPC5554是面向嵌入式系统设计的专业微控制器，广泛应用于汽车电子、工业自动化和其他需要高性能和低功耗的领域。 **MPC5553/MPC5554 微控制器特性：** 1. **处理器核心**: 这些微控制器基于Power Architecture技术，提供高效的处理能力，支持实时操作系统（RTOS）和复杂的算法执行。 2. **内存结构**: 内置多种内存类型，包括闪存、SRAM和EEPROM，以满足不同存储需求。闪存用于存储程序代码，SRAM用于运行时数据和程序变量，而EEPROM则用于非易失性数据存储。 3. **外设接口**: MPC5553和MPC5554集成了多种外设接口，如CAN（控制器局域网）、SPI（串行外围接口）、I²C（集成电路互连总线）、UART（通用异步收发传输器），以及GPIO（通用输入/输出）等，方便与外部设备通信。 4. **模拟功能**: 集成ADC（模数转换器）、DAC（数模转换器）和多种比较器，为系统提供强大的模拟信号处理能力。 5. **电源管理**: 支持多种电源模式，包括低功耗模式，以适应不同应用场合，优化能源效率。 6. **安全特性**: 设计有安全特性，如加密引擎，用于保护代码安全和防止未经授权的访问。 **文档内容与使用注意事项：** - **信息使用许可**: 该文档提供的信息仅供系统和软件实施者使用Freescale Semiconductor产品，不授予设计或制造任何集成电路或基于文档信息的集成电路的版权许可。 - **变更通知**: Freescale Semiconductor保留在不另行通知的情况下对任何产品进行更改的权利，并不对其产品的适用性或因使用产品或电路产生的任何责任作出任何保修、陈述或保证。 - **典型参数**: 文档中可能提供的“典型”参数可能在不同应用中有所变化，实际性能会随时间变化。操作参数应在具体应用中验证。 - **应用与使用风险**: 用户应自行承担使用这些产品或电路可能导致的任何损害，包括但不限于间接或附带损害。 **开发与调试工具：** 为了有效利用MPC5553和MPC5554微控制器，开发者通常需要配合使用开发板、仿真器、IDE（集成开发环境）以及相应的软件库。这些工具可以帮助程序员快速编写、调试和优化代码，同时简化硬件接口的配置。 **总结：** MPC5553和MPC5554参考手册是理解并利用这些微控制器进行系统设计的关键资源。它提供了详细的硬件描述、外设接口的使用方法以及操作参数，是工程师开发基于这些器件的嵌入式系统的必备参考资料。开发者应仔细阅读并理解文档中的各项内容，以确保正确、安全地使用这些微控制器。

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 3.1

xvi Freescale Semiconductor

Contents

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11.1.4.2 External Reference Mode ................................................................................... 11-11

11.1.4.3 Bypass Mode ...................................................................................................... 11-11

11.1.4.4 Dual-Controller Mode (1:1) ................................................................................ 11-11

11.2 External Signal Description ........................................................................................ 11-12

11.3 Memory Map/Register Definition .............................................................................. 11-12

11.3.1 Register Descriptions .............................................................................................. 11-12

11.3.1.1 Synthesizer Control Register (FMPLL_SYNCR) .............................................. 11-12

11.3.1.2 Synthesizer Status Register (FMPLL_SYNSR) ................................................. 11-16

11.4 Functional Description ................................................................................................ 11-19

11.4.1 Clock Architecture .................................................................................................. 11-19

11.4.1.1 Overview ............................................................................................................. 11-19

11.4.1.2 Software Controlled Power Management/Clock Gating .................................... 11-19

11.4.1.3 Clock Dividers .................................................................................................... 11-20

11.4.2 Clock Operation ...................................................................................................... 11-21

11.4.2.1 Input Clock Frequency ....................................................................................... 11-21

11.4.2.2 Reduced Frequency Divider (RFD) .................................................................... 11-21

11.4.2.3 Programmable Frequency Modulation ............................................................... 11-21

11.4.2.4 FMPLL Lock Detection ...................................................................................... 11-22

11.4.2.5 FMPLL Loss-of-Lock Conditions ...................................................................... 11-22

11.4.2.6 Loss-of-Clock Detection ..................................................................................... 11-23

11.4.3 Clock Configuration ............................................................................................... 11-24

11.4.3.1 Programming System Clock Frequency Without Frequency Modulation ......... 11-24

11.4.3.2 Programming System Clock Frequency with Frequency Modulation ............... 11-25

11.4.3.3 FM Calibration Routine ...................................................................................... 11-27

11.5 Revision History ......................................................................................................... 11-31

Chapter 12

External Bus Interface (EBI)

12.1 Introduction ................................................................................................................... 12-1

12.1.1 Block Diagram .......................................................................................................... 12-2

12.1.2 Overview ................................................................................................................... 12-2

12.1.3 Features ..................................................................................................................... 12-3

12.1.4 Modes of Operation .................................................................................................. 12-4

12.1.4.1 Single Master Mode .............................................................................................. 12-4

12.1.4.2 External Master Mode .......................................................................................... 12-4

12.1.4.3 Module Disable Mode .......................................................................................... 12-5

12.1.4.4 Configurable Bus Speed Modes ........................................................................... 12-5

12.1.4.5 16-Bit Data Bus Mode .......................................................................................... 12-5

12.1.4.6 Debug Mode ......................................................................................................... 12-5

12.2 External Signal Description .......................................................................................... 12-6

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 3.1

Freescale Semiconductor xvii

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12.2.1 Detailed Signal Descriptions .................................................................................... 12-6

12.2.1.1 Address Lines 8–31 (ADDR[8:31]) ..................................................................... 12-6

12.2.1.2 Bus Busy (BB) — MPC5554 Only ...................................................................... 12-7

12.2.1.3 Burst Data in Progress (BDIP) ............................................................................ 12-7

12.2.1.4 Bus Grant (BG) — MPC5554 Only ..................................................................... 12-7

12.2.1.5 Bus Request (BR) — MPC5554 Only .................................................................. 12-7

12.2.1.6 Clockout (CLKOUT) ............................................................................................ 12-8

12.2.1.7 Chip Selects 0–3 (CS[0:3]) ................................................................................... 12-8

12.2.1.8 Calibration Chip Selects 0, 2-3 (CAL_CS [0], CAL_CS [2:3]) - MPC5553 Only 12-8

12.2.1.9 Data Lines 0–31 (DATA[0:31]) ........................................................................... 12-8

12.2.1.10 Output Enable (OE) .............................................................................................. 12-8

12.2.1.11 Read / Write (RD_WR) ........................................................................................ 12-9

12.2.1.12 Transfer Acknowledge (TA) ................................................................................. 12-9

12.2.1.13 Transfer Error Acknowledge (TEA) ..................................................................... 12-9

12.2.1.14 Transfer Start (TS) ................................................................................................ 12-9

12.2.1.15 Transfer Size 0–1 (TSIZ[0:1]) — MPC5554 Only ............................................... 12-9

12.2.1.16 Write/Byte Enables (WE / BE) ........................................................................... 12-10

12.2.2 Signal Function/Direction by Mode ....................................................................... 12-11

12.2.3 Signal Pad Configuration by Mode ........................................................................ 12-12

12.3 Memory Map/Register Definition .............................................................................. 12-14

12.3.1 Register Descriptions .............................................................................................. 12-14

12.3.1.1 Writing EBI Registers While a Transaction is in Progress ................................. 12-14

12.3.1.2 Separate Input Clock for Registers .................................................................... 12-15

12.3.1.3 EBI Module Configuration Register (EBI_MCR) .............................................. 12-15

12.3.1.4 EBI Transfer Error Status Register (EBI_TESR) ............................................... 12-17

12.3.1.5 EBI Bus Monitor Control Register (EBI_BMCR) ............................................. 12-17

12.3.1.6 EBI Base Registers 0–3 (EBI_BRn) and EBI Calibration Base Registers 0–3

(EBI_CAL_BRn) ............................................................................................ 12-18

12.3.1.7 EBI Option Registers 0–3 (EBI_ORn) and EBI Calibration Option Registers 0-3

(EBI_CAL_ORn) ............................................................................................ 12-20

12.4 Functional Description ................................................................................................ 12-21

12.4.1 External Bus Interface Features .............................................................................. 12-21

12.4.1.1 32-Bit Address Bus with Transfer Size Indication ............................................. 12-21

12.4.1.2 32-Bit Data Bus .................................................................................................. 12-22

12.4.1.3 16-Bit Data Bus .................................................................................................. 12-22

12.4.1.4 Support for External Master Accesses to Internal Addresses ............................. 12-22

12.4.1.5 Memory Controller with Support for Various Memory Types .......................... 12-22

12.4.1.6 Burst Support (Wrapped Only) ........................................................................... 12-23

12.4.1.7 Bus Monitor ........................................................................................................ 12-24

12.4.1.8 Port Size Configuration per Chip Select (16 or 32 Bits) .................................... 12-24

12.4.1.9 Port Size Configuration per Calibration Chip Select (16 Bits) ........................... 12-24

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 3.1

xviii Freescale Semiconductor

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12.4.1.10 Configurable Wait States .................................................................................... 12-24

12.4.1.11 Four Chip Select (CS[0:3]) Signals .................................................................... 12-24

12.4.1.12 Support for Dynamic Calibration with Up to 4 Chip Selects ............................. 12-24

12.4.1.13 Four Write/Byte Enable (WE/BE) Signals — Only MPC5554 and 416 BGA of

MPC5553 ........................................................................................................ 12-24

12.4.1.14 Two Write/Byte Enable (WE/BE) Signals — 324 BGA of MPC5553 Only ..... 12-25

12.4.1.15 Configurable Bus Speed Clock Modes ............................................................... 12-26

12.4.1.16 Stop and Module Disable Modes for Power Savings ......................................... 12-26

12.4.1.17 Optional Automatic CLKOUT Gating ............................................................... 12-26

12.4.1.18 Compatible with MPC5xx External Bus

(with Some Limitations) ................................................................................. 12-27

12.4.2 External Bus Operations ......................................................................................... 12-27

12.4.2.1 External Clocking ............................................................................................... 12-27

12.4.2.2 Reset ................................................................................................................... 12-27

12.4.2.3 Basic Transfer Protocol ...................................................................................... 12-27

12.4.2.4 Single Beat Transfer ........................................................................................... 12-28

12.4.2.5 Burst Transfer ..................................................................................................... 12-35

12.4.2.6 Small Accesses (Small Port Size and Short Burst Length) ................................ 12-40

12.4.2.7 Size, Alignment, and Packaging on Transfers .................................................... 12-43

12.4.2.8 Arbitration ........................................................................................................... 12-45

12.4.2.9 Termination Signals Protocol ............................................................................. 12-52

12.4.2.10 Bus Operation in External Master Mode ............................................................ 12-54

12.4.2.11 Non-Chip-Select Burst in 16-bit Data Bus Mode ............................................... 12-65

12.4.2.12 Calibration Bus Operation — MPC5553 Only ................................................... 12-67

12.5 Initialization/Application Information ........................................................................ 12-68

12.5.1 Booting from External Memory ............................................................................. 12-68

12.5.2 Running with SDR (Single Data Rate) Burst Memories ........................................ 12-68

12.5.3 Running with Asynchronous Memories ................................................................. 12-68

12.5.3.1 Example Wait State Calculation ......................................................................... 12-69

12.5.3.2 Timing and Connections for Asynchronous Memories ...................................... 12-69

12.5.4 Connecting an MCU to Multiple Memories ........................................................... 12-71

12.5.5 Dual-MCU Operation with Reduced Pinout MCUs ............................................... 12-71

12.5.5.1 Connecting 16-bit MCU to 32-bit MCU (Master/Master or Master/Slave) ....... 12-71

12.5.5.2 Arbitration with No Arb Pins (Master/Slave only) ............................................. 12-72

12.5.5.3 Transfer Size with No TSIZ Pins (Master/Master or Master/Slave) .................. 12-72

12.5.5.4 No Transfer Acknowledge (TA) Pin .................................................................. 12-72

12.5.5.5 No Transfer Error (TEA) Pin .............................................................................. 12-72

12.5.5.6 No Burst Data in Progress (BDIP) Pin ............................................................... 12-72

12.5.6 Summary of Differences from MPC5xx ................................................................. 12-72

12.6 Revision History ......................................................................................................... 12-73

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 3.1

Freescale Semiconductor xix

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Chapter 13

Flash Memory

13.1 Introduction ................................................................................................................... 13-1

13.1.1 Block Diagram .......................................................................................................... 13-1

13.1.2 Overview ................................................................................................................... 13-1

13.1.3 Features ..................................................................................................................... 13-3

13.1.4 Modes of Operation .................................................................................................. 13-3

13.1.4.1 User Mode ............................................................................................................ 13-3

13.1.4.2 Stop Mode ............................................................................................................. 13-3

13.2 External Signal Description .......................................................................................... 13-4

13.2.1 Voltage for Flash Only (V

FLASH

) ............................................................................. 13-4

13.2.2 Program and Erase Voltage for Flash Only (V

) .................................................... 13-4

13.3 Memory Map/Register Description .............................................................................. 13-4

13.3.1 Flash Memory Map ................................................................................................... 13-5

13.3.2 Register Descriptions ................................................................................................ 13-8

13.3.2.1 Module Configuration Register (FLASH_MCR) ................................................. 13-8

13.3.2.2 Low/Mid Address Space Block Locking Register (FLASH_LMLR) ................ 13-12

13.3.2.3 High Address Space Block Locking Register (FLASH_HLR) .......................... 13-14

13.3.2.4 Secondary Low/Mid Address Space Block Locking Register (FLASH_SLMLR).......

13-15

13.3.2.5 Low/Mid Address Space Block Select Register (FLASH_LMSR) .................... 13-16

13.3.2.6 High Address Space Block Select Register (FLASH_HSR) .............................. 13-17

13.3.2.7 Address Register (FLASH_AR) ......................................................................... 13-19

13.3.2.8 Flash Bus Interface Unit Control Register (FLASH_BIUCR) ........................... 13-19

13.3.2.9 Flash Bus Interface Unit Access Protection Register (FLASH_BIUAPR) ........ 13-22

13.4 Functional Description ................................................................................................ 13-23

13.4.1 Flash Bus Interface Unit (FBIU) ............................................................................ 13-23

13.4.1.1 FBIU Basic Interface Protocol ............................................................................ 13-23

13.4.1.2 FBIU Access Protections .................................................................................... 13-23

13.4.1.3 Flash Read Cycles—Buffer Miss ....................................................................... 13-24

13.4.1.4 Flash Read Cycles—Buffer Hit .......................................................................... 13-24

13.4.1.5 Flash Access Pipelining ...................................................................................... 13-24

13.4.1.6 Flash Error Response Operation ......................................................................... 13-24

13.4.1.7 FBIU Line Read Buffers and Prefetch Operation ............................................... 13-24

13.4.1.8 FBIU Instruction/Data Prefetch Triggering ........................................................ 13-25

13.4.1.9 FBIU Per-Master Prefetch Triggering ................................................................ 13-25

13.4.1.10 FBIU Buffer Invalidation ................................................................................... 13-25

13.4.1.11 Flash Wait-state Emulation ................................................................................. 13-25

13.4.2 Flash Memory Array: User Mode .......................................................................... 13-25

13.4.2.1 Flash Read and Write .......................................................................................... 13-26

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 3.1

xx Freescale Semiconductor

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13.4.2.2 Read While Write (RWW) ................................................................................. 13-26

13.4.2.3 Flash Programming ............................................................................................. 13-28

13.4.2.4 Flash Erase .......................................................................................................... 13-31

13.4.2.5 Flash Shadow Block ........................................................................................... 13-35

13.4.2.6 Censorship .......................................................................................................... 13-35

13.4.3 Flash Memory Array: Stop Mode ........................................................................... 13-37

13.4.4 Flash Memory Array: Reset .................................................................................... 13-37

13.5 Revision History ......................................................................................................... 13-38

Chapter 14

Fast Ethernet Controller (FEC)

14.1 Introduction ................................................................................................................... 14-1

14.1.1 Block Diagram .......................................................................................................... 14-2

14.1.2 Overview ................................................................................................................... 14-3

14.1.3 Features ..................................................................................................................... 14-3

14.2 Modes of Operation ...................................................................................................... 14-4

14.2.1 Full and Half Duplex Operation ............................................................................... 14-4

14.2.2 Interface Options ....................................................................................................... 14-4

14.2.2.1 10 Mbps and 100 Mbps MII Interface .................................................................. 14-4

14.2.2.2 10 Mpbs 7-Wire Interface Operation .................................................................... 14-5

14.2.3 Address Recognition Options ................................................................................... 14-5

14.2.4 Internal Loopback ..................................................................................................... 14-5

14.3 Programming Model ..................................................................................................... 14-5

14.3.1 Top Level Module Memory Map ............................................................................. 14-5

14.3.2 Detailed Memory Map (Control/Status Registers) ................................................... 14-6

14.3.3 MIB Block Counters Memory Map .......................................................................... 14-7

14.3.4 Registers .................................................................................................................. 14-10

14.3.4.1 FEC Burst Optimization Master Control Register (FBOMCR) (MPC5553 Only) .......

14-10

14.3.4.2 FEC Registers ..................................................................................................... 14-12

14.3.4.3 FIFO Receive Bound Register (FRBR) .............................................................. 14-31

14.4 Functional Description ................................................................................................ 14-35

14.4.1 Initialization Sequence ............................................................................................ 14-35

14.4.1.1 Hardware Controlled Initialization ..................................................................... 14-35

14.4.2 User Initialization (Prior to Asserting ECR[ETHER_EN]) .................................... 14-36

14.4.3 Microcontroller Initialization .................................................................................. 14-37

14.4.4 User Initialization (After Asserting ECR[ETHER_EN]) ....................................... 14-37

14.4.5 Network Interface Options ...................................................................................... 14-37

14.4.6 FEC Frame Transmission ....................................................................................... 14-38

14.4.7 FEC Frame Reception ............................................................................................. 14-39

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