tm4c123gh6pz数据手册思维导图：快速掌握寄存器与功能

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"TM4C123GH6PZ是一款高性能微控制器，它基于Cortex-M系列架构，具备80MHz的时钟速度和集成FPU，提供出色的性能。该设备的数据手册通过思维导图的形式整理，旨在帮助用户快速理解和掌握其功能、编程以及寄存器操作。首先，关于寄存器部分，TM4C123GH6PZ拥有多种类型的可读写寄存器，如RC（Read-Clear by Hardware after Reading the Bit/Field），用于在读取后由硬件自动清零；RO（Only Read）仅允许读取，确保数据的只读性；RW、RWC、RW1C、RW1S、W1C等寄存器类型支持读写操作，各有特定功能，如RW1C主要用于清除中断状态位，而W1C则用于单独清除某位。信号管理是TM4C123GH6PZ的另一个关键特性，信号可以被激活或去激活，激活状态可以通过高电平或低电平表示，这对于控制外部电路和通信非常重要。例如，assert信号用于设置逻辑状态，而deassert则用于撤销信号。硬件规格方面，TM4C123GH6PZ配备了80MHz的Cortex-M处理器，具备100DMIPS的运算能力，即每秒执行100百万条指令，这使得它在处理密集型任务时表现出色。此外，FPU的存在使其能够执行浮点运算，进一步增强了处理复杂算法的能力。 TM4C123GH6PZ数据手册的思维导图形式提供了一个清晰的结构，无论是初学者还是经验丰富的开发人员，都能快速找到他们需要的信息，进行高效的开发和调试工作。通过理解这些寄存器的特性和信号的行为，开发者能够充分利用这款微控制器的强大功能，实现高效稳定的系统设计。"

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6.5.2. Late-Arriving .........................................................................................62
6.5.3. Tail-Chaining .........................................................................................62
6.5.4. Return...................................................................................................62
6.5.5. Exception Entry.....................................................................................62
6.5.6. Exception Return ..................................................................................63
EXC_RETURN is the value loaded into the LR on exception entry ....................63
EXC_RETURN bits 31:5 are all set. When this value is loaded into the PC, it 
indicates to the processor  that the exception is complete, and the processor 
initiates the appropriate exception return sequence .......................................63
7. Instruction Set Summary ...................................................................................63
7.1. 2.8 附表 .......................................................................................................63
ADC ............................................................................................................................63
1. Subtopic 1 ..........................................................................................................63
PWM ..........................................................................................................................64
Programmable GPIOs.................................................................................................64
Watchdog Timers.......................................................................................................64
Programmable Timers ...............................................................................................64
System Control and Clocks ........................................................................................64
1. Device identification information......................................................................64
1.1. version, part number, SRAM size, Flash memory size, and so on...............64
1.1.1. Device Identification 0 (DID0) ..............................................................64
1.1.2. Device Identification 1 (DID1) ..............................................................64
1.2. information about the capabilities of the on-chip peripherals are provided 
at offset 0xFC0 in each peripheral's register space...................................................64
1.2.1. such as the GPTM Peripheral Properties (GPTMPP) register...............64
1.3. Device Capabilities (DC0-DC9) registers ......................................................64
2. Power control ....................................................................................................64
2.1. On-chip fixed Low Drop-Out (LDO) voltage regulator .................................64
2.2. Hibernation module handles the power-up/down 3.3 V sequencing and 
control for the core  digital logic and analog circuits ................................................65
3. clock source .......................................................................................................65
3.1. Precision Internal Oscillator (PIOSC)............................................................65
3.1.1. 16 MHz ±3%..........................................................................................65
3.1.2. Software power down control for low power modes..........................65
3.1.3. the PIOSC can be configured to be the source for the ADC clock as well 
as the baud clock for the UART and SSI.................................................................65
3.1.4. the PIOSC must remain enabled as it is used for internal functions....65
3.1.5. calibration.............................................................................................65
Automatic calibration using the Hibernation module with a functioning 
768-kHz clock source ....................................................................................65
User-defined calibration ....................................................................................65
Default calibration: clear the UTEN bit and set the UPDATE bit in the Precision 
Internal Oscillator  Calibration (PIOSCCAL) register ..........................................65
3.2. Main Oscillator (MOSC) ...............................................................................65

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9.3.2.1. an external single-ended clock source is connected to the OSC0 input 
pin 66
pin65:osc0..........................................................................................................66
9.3.2.2. an external crystal is  connected across the OSC0 input and OSC1 
output pins.............................................................................................................66
pin66 :osc1.........................................................................................................66
9.3.2.3. to use PLL..............................................................................................66
the crystal value must be one of the supported frequencies between 5 MHz to 
25 MHz...............................................................................................................66
9.3.2.4. XTAL bit field in the RCC register..........................................................66
Software configures the RCC register XTAL field with the crystal number .......66
9.3.2.5. the clock source for the USB PLL ..........................................................66
usb module  must use the MOSC either whit or without PLL the system clock 
must be at least 20MHz.....................................................................................66
9.3.2.6. Main Oscillator Verification Circuit ......................................................66
enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL) register
...........................................................................................................................66
9.3.3. Low Frequency Internal Oscillator (LFIOSC) ................................................66
9.3.3.1. On-chip resource used during power-saving  modes ..........................66
9.3.4. Hibernate RTC oscillator (RTCOSC) clock.....................................................66
9.3.4.1. can be configured to be the 32.768-kHz external oscillator source from 
the Hibernation (HIB) module ...............................................................................67
9.3.4.2. HIB Low Frequency clocksource (HIB LFIOSC), which is located within 
the Hibernation Module ........................................................................................67
9.3.5. 6 个 system closk (SysClk ) source ...............................................................67
9.3.5.1. internal system clock (SysClk), is derived from any of the above 
sources plus two others: the  output of the main internal PLL and the precision 
internal oscillator divided by four (4 MHz ± 1%). 四个时钟源 + PLL + PIOSC/4...67
9.3.5.2. Clock Configuration ..............................................................................67
Run-Mode Clock Configuration (RCC)................................................................68
Run-Mode Clock Configuration 2 (RCC2)...........................................................68
The peripheral blocks are driven by the system clock signal and can be 
individually enabled/disabled............................................................................68
The ADC clock signal can be selected from the PIOSC, the system clock if the 
PLL is disabled,  or the PLL output divided down to 16 MHz if the PLL is 
enabled ..............................................................................................................69
The PWM clock signal is a synchronous divide of the system clock to provide 
the PWM circuit with more range (set with PWMDIV in RCC)..........................69
the UART, and SSI modules all have a Clock Control register in the peripheral's 
register map at offset 0xFC8 that can be used to select the clock source for the 
module's baud clock ..........................................................................................69
9.4. reset sources......................................................................................................69

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9.4.1. -  Power-on reset (POR) – Reset pin assertion – Brown-out reset (BOR) 
detector alerts to system power drops – Software reset – Watchdog timer reset – 
MOSC failure ..............................................................................................................69
9.4.1.1. V DD under BOR0. ................................................................................69
9.4.1.2. VDD under BOR1 ..................................................................................69
Power-On and Brown-Out Reset Control (PBORCTL) ........................................69
清空寄存器的这两个位可以用BOR事件来产生中断 ....................................70
9.4.1.3. software system request reset.............................................................70
APINT .................................................................................................................70
Peripherals can be individually reset by software via peripheral-specific reset 
registers available  beginning at System Control offset 0x500 (for example the 
Watchdog Timer Software Reset  (SRWD) register). .........................................70
9.4.1.4. For applications that require the use of an external reset signal to hold 
the microcontroller in reset longer than the internal POR ...................................70
the core loads from memory the initial stack pointer, the initial program 
counter, and the first instruction designated by the program counter, and then 
begins  execution ...............................................................................................70
9.4.1.5. The watchdog  timer can be configured to generate an interrupt or a 
non-maskable interrupt to the microcontroller  on its first time-out and to 
generate a reset on its second time-out. ..............................................................70
Watchdog Timer Load (WDTLOAD)  register.....................................................70
9.4.2. rst:  pin 63 ....................................................................................................71
9.4.3. Reset Cause (RESC) register.........................................................................71
9.4.3.1. After a reset, the Reset Cause (RESC) register is set with the reset 
cause 71
9.4.3.2. can be cleared by writing a 0................................................................71
9.4.4. Boot  Configuration (BOOTCFG) register .....................................................71
9.4.4.1. At any reset that resets the core, the user has the opportunity to 
direct the core to execute the ROM Boot Loader or the application in Flash 
memory by using any GPIO signal as configured in it ...........................................71
9.4.4.2. 这个寄存器可配置系统复位后执行Boot loader 还是 application in 
flash 71
At reset, the following sequence is performed: 1. The BOOTCFG register is 
read. If the EN bit is clear, the ROM Boot Loader is executed. 2. In the ROM 
Boot Loader, the status of the specified GPIO pin is compared with the 
specified polarity. If the status matches the specified polarity, the ROM is 
mapped to address 0x0000.0000 and execution continues out of the ROM 
Boot Loader. 3. f then EN bit is set or the status doesn't match the specified 
polarity, the data at address 0x0000.0004 is read, and if the data at this 
address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and 
execution continues out of the ROM Boot Loader. 4. If there is data at address 
0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded from 
Flash memory at address 0x0000.0000 and the program counter (PC) is loaded 

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from address 0x0000.0004. The user application begins executing. Note: If the 
device fails the initialization phase, it toggles the TDO output pin as an 
indication the device is not executing. This feature is provided for debug 
purposes. ...........................................................................................................71
EN:  0..................................................................................................................72
EN:  1..................................................................................................................72
9.4.4.3. The DBG0 and DBG1 bits of the Boot Configuration (BOOTCFG) 
register control whether the debug  interface is turned on or off........................72
Disabling the debug interface is permanent and cannot be reversed ..............72
9.5. NMI ....................................................................................................................72
9.5.1. four sources of non-maskable interrupt (NMI) ...........................................72
9.5.1.1. The assertion of the NMI signal ...........................................................72
pin 40  PD7  /  pin 100  PF0  (input) ...................................................................73
9.5.1.2. A main oscillator verification error ......................................................73
The detection circuit is enabled by setting the CVAL bit in the Main Oscillator 
Control (MOSCCTL) register...............................................................................73
9.5.1.3. The NMISET bit in the Interrupt Control and State (INTCTRL) register in 
the Cortex™-M4F ...................................................................................................73
9.5.1.4. The Watchdog module time-out interrupt when the INTTYPE bit in the 
Watchdog Control   (WDTCTL) register is set ........................................................73
9.6. system control ...................................................................................................73
9.6.1. There must be a delay of 3 system clocks after a peripheral module clock is 
enabled in the RCGC register before any module registers are accessed ................73
9.6.1.1. 使用外设必须通过寄存器对其时钟使能 ..........................................73
9.6.2. register map.................................................................................................73
9.6.2.1. base:  table 2-4 /  0x400FE000 .............................................................73
9.6.2.2. talbe 5-7................................................................................................73

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