Xilinx Spartan-3配置详解

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"这是一份关于Spartan3 FPGA配置的详尽指南，适用于Extended Spartan-3A、Spartan-3E以及Spartan-3系列。文档由Xilinx公司发布，旨在帮助用户在与Xilinx硬件设备配合时进行设计开发。" Spartan-3系列是Xilinx公司推出的一系列现场可编程门阵列（FPGA），它提供了经济高效的解决方案，广泛应用于各种嵌入式系统、数字信号处理(DSP)和通用逻辑应用中。本配置指南针对Spartan-3 Generation，包括Extended Spartan-3A、Spartan-3E和Spartan-3 FPGA家族，为开发者提供了全面的配置指导。配置Spartan-3 FPGA涉及以下几个核心知识点： 1. **配置流程**：通常包括下载配置数据到配置器件、初始化配置过程、加载配置数据到FPGA逻辑单元以及启动FPGA工作等步骤。这个过程可能通过JTAG（Joint Test Action Group）接口、串行配置存储器或并行配置方式来实现。 2. **配置器件**：Spartan-3 FPGA支持多种配置器件，如SRAM型配置器件、E2PROM或闪存。这些器件存储了编程的比特流，用于初始化FPGA的逻辑功能。 3. **配置模式**：Spartan-3系列支持多种配置模式，如即时启动（In-System Programming, ISP）、并行加载（Parallel Load）、串行加载（Serial Load）等，每种模式有其特定的应用场景和优势。 4. **设计工具**：使用Xilinx的Vivado或ISE等设计套件，可以生成适用于Spartan-3 FPGA的配置比特流文件。这些工具提供了逻辑综合、布局布线、时序分析等功能，确保设计满足性能要求。 5. **约束文件**：在设计过程中，约束文件（如UCF或XDC）用于定义外部引脚分配、时钟和其他硬件特性，确保设计符合硬件平台的具体需求。 6. **错误处理和更新**：Xilinx强调文档中可能存在的错误或遗漏，他们保留不事先通知即修改文档的权利，且不承担由于技术支持或协助过程中可能出现的任何错误或更新的责任。 7. **知识产权保护**：Xilinx文档的使用条款限制了对文档的复制、分发和公开展示，要求在使用时得到Xilinx的明确许可，以保护知识产权。通过这份Spartan-3配置用户指南，开发者能够学习到如何正确地配置和优化Spartan-3 FPGA，确保设计能够高效、稳定地运行在目标硬件上。对于那些初次接触FPGA或者Spartan-3系列的工程师来说，这份文档无疑是一份宝贵的参考资料。

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Figure 3-13: Generate PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 3-14: Program Platform Flash PROM using JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 3-15: iMPACT Automatically Detects JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 3-16: Bypass Programming the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 3-17: Select the Platform Flash Programming File . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 3-18: Program the Platform Flash PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 3-19: PROM Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Chapter 4: Master SPI Mode

Figure 4-1: SPI Flash Configuration Interface for M25P-compatible Devices . . . . . . . . 102

Figure 4-2: SPI Flash Configuration Interface for Atmel DataFlash Devices. . . . . . . . . 103

Figure 4-3: SPI Flash PROM/FPGA Power-On Timing if 3.3V

Supply is Last in Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 4-4: If Not Using SPI after Configuration, Drive CSO_B Pin High. . . . . . . . . . . 116

Figure 4-5: Using the SPI Flash Interface After Configuration . . . . . . . . . . . . . . . . . . . . . 117

Figure 4-6: Daisy Chaining from SPI Flash Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 4-7: Multiple, Identical FPGAs Programmed with the Same Bitstream . . . . . . . 120

Figure 4-8: Using FPGA’s JTAG Test Chain to Program Attached SPI Flash . . . . . . . . 125

Figure 4-9: Double-click Generate PROM, ACE or JTAG File . . . . . . . . . . . . . . . . . . . . . 126

Figure 4-10: Prepare a PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 4-11: Set Options for a 3rd-Party SPI PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 4-12: Select SPI PROM Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 4-13: Review PROM Formatting Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 4-14: Add FPGA Configuration Bitstream File(s) . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 4-15: Generate PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 4-16: iMPACT Supports Direct Programming for SPI Serial Flash Memories. 131

Figure 4-17: Select a Previously-formatted PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 4-18: Select a Supported SPI Flash Memory Device. . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 4-19: Directly Program Supported SPI Flash PROM.. . . . . . . . . . . . . . . . . . . . . . . 133

Figure 4-20: SPI PROM Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 4-21: Indirect Programming Method Uses JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 4-22: Select the FPGA Bitstream File and Enable SPI Programming . . . . . . . . . 135

Figure 4-23: iMPACT Uses the JTAG Clock Input TCK for Startup Clock when

Programming via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 4-24: Select the SPI PROM Programming FIle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 4-25: Select SPI Flash PROM Type

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 4-26: Bypass the Platform Flash PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 4-27: iMPACT Presents JTAG Chain, Shows Attached Flash PROM . . . . . . . . . 137

Figure 4-28: SPI PROM Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 4-29: Waveforms for Serial Peripheral Interface (SPI) Configuration . . . . . . . . 139

Figure 4-30: Multi-Package Layout for the M25Pxx Family on Spartan-3E Starter Kit 142

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Chapter 5: Master BPI Mode

Figure 5-1: Spartan-3E FPGA Configured from Parallel NOR Flash . . . . . . . . . . . . . . . . 144

Figure 5-2: Extended Spartan-3A Family FPGA Configured from

Parallel NOR Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 5-3: FPGA Supports x8 Interface before Configuration and Optional

x16 Interface after Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 5-4: Parallel Daisy Chain using BPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 5-5: Serial Daisy Chains are Only Available for

Extended Spartan-3A Family BPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 5-6: Master BPI Mode Using Xilinx

Parallel Platform Flash PROMs (XCFxxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 5-7: Double-click Generate PROM, ACE or JTAG File . . . . . . . . . . . . . . . . . . . . . 161

Figure 5-8: Prepare a PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 5-9: Set Options for a Generic Parallel PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 5-10: Select Parallel PROM Size and Configuration Style . . . . . . . . . . . . . . . . . . 164

Figure 5-11: Select FPGA Bitstream Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 5-12: Generate Parallel PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 5-13: Parallel NOR Flash PROM/FPGA Power-On Timing if 3.3V Supply

is Last in Power-On Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 5-14: BPI Configuration Timing Waveform

(Spartan-3E BPI Down mode shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Chapter 6: Master Parallel Mode

Chapter 7: Slave Parallel (SelectMAP) Mode

Figure 7-1: Slave Parallel Mode

(Spartan-3E and Extended Spartan-3A Family FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 7-2: Slave Parallel Mode (Spartan-3 FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 7-3: Slave Parallel Daisy Chain for

Spartan-3E/Extended Spartan-3A Family FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 7-4: Slave Parallel Daisy Chain Using Any Modern Xilinx FPGA . . . . . . . . . . . 182

Figure 7-5: SelectMAP Continuous Data Loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 7-6: SelectMAP Non-Continuous Data Loading with Controlled CSI_B. . . . . . 185

Figure 7-7: Non-Continuous SelectMAP Data Loading with Controlled CCLK. . . . . . 186

Figure 7-8: Configuration Abort Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 7-9: Readback Abort Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 7-10: Byte Swapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Chapter 8: Slave Serial Mode

Figure 8-1: Slave Serial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Chapter 9: JTAG Configuration Mode and Boundary-Scan

Figure 9-1: JTAG Configuration Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 9-2: Typical JTAG (IEEE 1149.1) Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

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Figure 9-3: Test Access Port (TAP) State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 9-4: Boundary-Scan Logic per I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 9-5: Spartan-3 Generation Boundary-Scan Timing Waveforms . . . . . . . . . . . . . . 207

Figure 9-6: Target Interface Connector Dimensions and Pin Assignments . . . . . . . . . . 208

Figure 9-7: Double-click Configure Device (iMPACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 9-8: Configure Devices Using JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 9-9: iMPACT Automatically Detects Devices on the JTAG Chain . . . . . . . . . . . 210

Figure 9-10: iMPACT Prompts for FPGA Bitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 9-11: iMPACT Automatically Adjusts FPGA Startup Clock

for JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 9-12: Click Bypass to Skip Platform Flash Programming . . . . . . . . . . . . . . . . . . . 211

Figure 9-13: Click Bypass to Skip CPLD Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Figure 9-14: Double-Click Program to Configure FPGA via JTAG . . . . . . . . . . . . . . . . . 212

Figure 9-15: FPGA Programming Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Chapter 10: Internal Master SPI Mode

Figure 10-1: Spartan-3AN FPGA using Internal Master SPI Flash Mode . . . . . . . . . . . . 215

Figure 10-2: Spartan-3AN SPI_ACCESS Design Primitive . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 10-3: Double-click Generate PROM, ACE or JTAG File . . . . . . . . . . . . . . . . . . . . 220

Figure 10-4: Prepare a PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 10-5: Set Options for Spartan-3AN In-System Flash PROM. . . . . . . . . . . . . . . . . 222

Figure 10-6: Select a Spartan-3AN FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 10-7: Specify the FPGA Configuration Bitstream(s) . . . . . . . . . . . . . . . . . . . . . . . . 224

Figure 10-8: Review Spartan-3AN In-System Memory Formatting Settings . . . . . . . . . 225

Figure 10-9: Add FPGA Configuration Bitstream File(s) . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Figure 10-10: iMPACT View of the Spartan-3AN In-System Flash Memory. . . . . . . . . 226

Figure 10-11: Generate the Spartan-3AN In-System Flash File. . . . . . . . . . . . . . . . . . . . . 226

Chapter 11: Configuration Bitstream Generator (BitGen) Settings

Chapter 12: Sequence of Events

Figure 12-1: Spartan-3 Generation FPGA Configuration Process. . . . . . . . . . . . . . . . . . . 239

Figure 12-2: FPGA Wake from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 12-3: Extended Spartan-3A Family and Spartan-3E Reset Circuitry

(Spartan-3 is similar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Figure 12-4: FPGA Power-Up Timing Waveforms (Master Modes). . . . . . . . . . . . . . . . . 242

Figure 12-5: Clear Configuration Memory (Initialization). . . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 12-6: Sample Control Pins (Mode Select, Variant Select) . . . . . . . . . . . . . . . . . . . 243

Figure 12-7: Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 12-8: Check Array ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 12-9: Load Configuration Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Figure 12-10: Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Figure 12-11: Startup Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

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Figure 12-12: Default Start-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 12-13: Extended Spartan-3A Family, Spartan-3E FPGA

Configuration Logic Conceptual Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Chapter 13: Configuration-Related Design Primitives

Figure 13-1: BSCAN Primitive for Extended Spartan-3A Family FPGAs . . . . . . . . . . . . 253

Figure 13-2: STARTUP Primitive for

Extended Spartan-3A Family and Spartan-3E FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 13-3: CAPTURE Primitive for Extended Spartan-3A Family FPGAs

(other families are similar). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 13-4: ICAP Primitive (only available on

Extended Spartan-3A Family FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 13-5: DNA_PORT Primitive

(only available on Extended Spartan-3A Family FPGAs) . . . . . . . . . . . . . . . . . . . . . . . 259

Chapter 14: Reconfiguration and MultiBoot

Figure 14-1: Example Spartan-3E MultiBoot Application

using 1Mbyte Parallel Flash PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Figure 14-2: Prepare a MultiBoot PROM Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 14-3: Select a PROM Supporting MultiBoot for Spartan-3E FPGAs . . . . . . . . . . 265

Figure 14-4: Select the Configuration Direction of the First MultiBoot Image . . . . . . . 266

Figure 14-5: Select a PROM Size and Add It to the Design . . . . . . . . . . . . . . . . . . . . . . . . 266

Figure 14-6: Confirm the PROM Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Figure 14-7: Select the First MultiBoot Configuration Image . . . . . . . . . . . . . . . . . . . . . . 267

Figure 14-8: Select the Second MultiBoot Configuration Image . . . . . . . . . . . . . . . . . . . 268

Figure 14-9: Generate the PROM File Using the Specified Parameters . . . . . . . . . . . . . 269

Figure 14-10: PROMGen Report File (*.prm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 14-11: Spartan-3A MultiBoot Example using XC3S700A and SPI Flash . . . . . . 279

Figure 14-12: Prepare a MultiBoot PROM Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 14-13: Select a PROM Supporting MultiBoot for

Extended Spartan-3A Family FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Figure 14-14: SPI or Parallel Flash PROMs are Supported . . . . . . . . . . . . . . . . . . . . . . . . 281

Figure 14-15: Enter a PROM Density and Specify MultiBoot Image Start Locations. . 281

Figure 14-16: Confirm PROM Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

Figure 14-17: Select the First (Default) Configuration Image . . . . . . . . . . . . . . . . . . . . . . 283

Figure 14-18: Select the Third MultiBoot Configuration Image . . . . . . . . . . . . . . . . . . . . 283

Figure 14-19: Generate the PROM File Using the Specified Parameters . . . . . . . . . . . . 284

Figure 14-20: Extended Spartan-3A Family MultiBoot Configuration Mode Control . 286

Chapter 15: Protecting FPGA Designs

Figure 15-1: Setting Bitstream Generator Options from ISE Project Navigator . . . . . . 291

Figure 15-2: Bitstream Generator Security Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Figure 15-3: Extended Spartan-3A Family DNA_PORT Design Primitive. . . . . . . . . . . 294

Figure 15-4: DNA_PORT Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

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Figure 15-5: Possible Options for DIN Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Figure 15-6: Extended Spartan-3A Family FPGA Configures Normally . . . . . . . . . . . . . 298

Figure 15-7: Extended Spartan-3A Family FPGA Authenticates the

PROM Image Against Device DNA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

Figure 15-8: Authentication Fails Using an Unauthorized Copy . . . . . . . . . . . . . . . . . . . 299

Figure 15-9: Spartan-3E FPGA Authentication Example using

Commodity Flash PROM with Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Figure 15-10: Spartan-3E FPGA Authenticates the PROM Image Against the

PROM’s Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Figure 15-11: Intelligent Host Downloads a Spartan-3A Bitstream . . . . . . . . . . . . . . . . . 302

Figure 15-12: Host Reads Device DNA, Generates Authentication Value . . . . . . . . . . . 302

Figure 15-13: Host Writes Authentication Value to Enable FPGA Application . . . . . . 302

Figure 15-14: FPGA Authentication Using SHA-1 Secure EEPROM . . . . . . . . . . . . . . . . 303

Figure 15-15: Extended Spartan-3A Family Device DNA

Used as a Key to Protect Embedded Processing Applications . . . . . . . . . . . . . . . . . . . 306

Chapter 16: Configuration CRC

Figure 16-1: Conceptual Overview of Post-Configuration CRC Calculator . . . . . . . . . . 311

Figure 16-2: UCF Constraints for Post-Configuration CRC . . . . . . . . . . . . . . . . . . . . . . . . 313

Figure 16-3: Checking Block RAM Contents Using Simple Parity . . . . . . . . . . . . . . . . . 315

Chapter 17: Configuration Details

Chapter 18: Readback

Figure 18-1: Changing the SelectMAP Port from Write to Read Control . . . . . . . . . . . . 332

Figure 18-2: SelectMAP Status Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Figure 18-3: IEEE 1532 JTAG Readback Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Figure 18-4: Readback Data Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

Figure 18-5: Comparing Readback Data Using the .msd and .rbd Files . . . . . . . . . . . . . 344

Figure 18-6: Comparing Readback Data Using the .msk and .bit Files . . . . . . . . . . . . . . 345

Figure 18-7: Extended Spartan-3A Library Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

Figure 18-8: Logic Allocation File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

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