DDR3L SDRAM MT41K1G8：1.35V低电压汽车级内存

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"MT41K1G8手册是关于DDR3L SDRAM的详细技术文档，主要讨论了这种低电压版本的内存芯片，其在1.35V工作模式下与标准DDR3（1.5V）SDRAM的兼容性。手册指出，虽然DDR3L运行在更低的电压下，但仍能与1.5V的系统兼容。同时，该手册适用于两种不同的内存配置：MT41K1G8（128Megx8x8 banks）和MT41K512M16（64Megx16x8 banks）。" DDR3L SDRAM是DDR3内存的一种优化版本，主要特点是工作电压降低至1.35V，相比传统的1.5V DDR3，它提供了更节能的解决方案。在1.5V兼容模式下，DDR3L内存可以按照DDR3 SDRAM的数据表规格运行，这意味着在不改变硬件设计的情况下，系统可以无缝地从1.5V内存切换到1.35V内存。此手册的特性部分列出了DDR3L SDRAM的关键功能： 1. **电压范围**：工作电压VDD和数据线电压VDDQ均为1.35V，允许的电压波动在1.283V到1.45V之间。 2. **兼容性**：向后兼容1.5V DDR3标准，支持DDR3L设备在1.5V环境中运行。 3. **数据传输**：采用差分双向数据 strobe，确保高速、低噪声的数据传输。 4. **架构**：8n位预取架构，提高数据处理效率。 5. **时钟输入**：使用差分时钟输入（CK和CK#），降低时钟信号的干扰。 6. **内部结构**：8个内部银行，增强了并发访问能力。 7. **动态输出阻抗匹配**：对数据、 strobe和mask信号进行可编程的开路动态阻抗匹配（ODT）。 8. **CAS延迟**：可编程的读取（CL）、写入（CWL）和附加（AL）CAS延迟，提供灵活的性能调整。 9. **突发长度**：固定突发长度BL为8，可通过模式寄存器集（MRS）选择4的突发切分（BC）。 10. **飞行中选择BL4或BL8**：在运行过程中动态选择突发长度。 11. **自刷新模式**：支持在不使用时保持数据完整性，节省功率。 12. **温度范围**：适用于0°C至+95°C的工作温度，具有特定的刷新周期要求。 13. **自刷新温度**（SRT）：根据温度自动调整刷新策略。 14. **自动自刷新**：自动执行自刷新操作，确保数据在不同环境下的稳定性。此外，手册还可能涵盖了关于封装、电气特性、测试条件、功耗、热管理、ESD保护、故障诊断和故障恢复等方面的内容，这些都是理解和使用这些内存芯片时必须考虑的关键因素。对于汽车电子等对温度和可靠性要求严格的领域，这些特性尤其重要。

Figure 4: 512 Meg x 16 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[15:0]

BA[2:0]

Address

(128

x128)

16,384

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(65,536 x 128 x 128)

Bank 0

row-

address

latch

and

decoder

65,536

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

128

LDQS, LDQS#, UDQS, UDQS#

Column 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

BC4

READ

drivers

DQ[15:0]

READ

FIFO

and

data

MUX

Data

BC4 (burst chop)

Bank 1

Bank 2

Bank 3

LDM/UDM

CK, CK#

LDQS, LDQS#

UDQS, UDQS#

ZQ CAL

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[15:0]

(1 . . . 16)

(1 . . . 4)

(1, 2)

sw1

sw2

DDQ

TT,nom

TT(WR)

BC4

sw1

sw2

DDQ

TT,nom

TT(WR)

sw1

sw2

DDQ

TT,nom

TT(WR)

Column 2

(select upper or

lower nibble for BC4)

Data

interface

WRITE

drivers

and

input

logic

ODT

control

SSQ

A12

OTF

8Gb: x8, x16 Automotive DDR3L SDRAM

Functional Block Diagrams

09005aef861cf5fa

auto_8Gb_DDR3L.pdf - Rev. F 05/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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Table 3: 78-Ball FBGA – x8 Ball Descriptions

Symbol Type Description

A[15:13], A12/BC#,

A11, A10/AP, A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one bank

(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also

provide the op-code during a LOAD MODE command. Address inputs are referenced

to V

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4). See the Truth Table – Com-

mand section.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode

BA[2:0] are referenced to V

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of

CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW)

internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/

disabled is dependent upon the DDR3 SDRAM configuration and operating mode.

Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations

(all banks idle), or active power-down (row active in any bank). CKE is synchronous

for power-down entry and exit and for self refresh entry. CKE is asynchronous for

self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are

disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disa-

bled during SELF REFRESH. CKE is referenced to V

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#

provides for external rank selection on systems with multiple ranks. CS# is considered

part of the command code. CS# is referenced to V

REFCA

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with the input data during a write access.

Although the DM ball is input-only, the DM loading is designed to match that of the

DQ and DQS balls. DM is referenced to V

REFDQ

. DM has an optional use as TDQS on

the x8.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal

operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,

and DM for the x8. The ODT input is

ignored if disabled via the LOAD MODE command. ODT is referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V

and

DC LOW ≤ 0.2 × V

DDQ

. RESET# assertion and desertion are asynchronous.

8Gb: x8, x16 Automotive DDR3L SDRAM

Ball Assignments and Descriptions

09005aef861cf5fa

auto_8Gb_DDR3L.pdf - Rev. F 05/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x8 Ball Descriptions (Continued)

Symbol Type Description

DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are

referenced to V

REFDQ

DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write

data. Center-aligned to write data.

TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only. When TDQS is

enabled, DM is disabled, and the TDQS and TDQS# balls provide termination

resistance.

Supply Power supply: 1.35V (1.283–1.45V) / 1.5V ±0.075V (backward compatible).

DDQ

Supply DQ power supply: 1.35V (1.283–1.45V) /1.5V ±0.075V (backward compatible). Isola-

ted on the device for improved noise immunity.

REFCA

Supply Reference voltage for control, command, and address: V

REFCA

must be

maintained at all times (including self refresh) for proper device operation.

REFDQ

Supply Reference voltage for data: V

REFDQ

must be maintained at all times (excluding self

refresh) for proper device operation.

Supply Ground.

SSQ

Supply DQ ground: Isolated on the device for improved noise immunity.

ZQ Reference External reference ball for output drive calibration: This ball is tied to an

external 240Ω resistor (RZQ), which is tied to V

SSQ

NC – No connect: These balls should be left unconnected (the ball has no connection to

the DRAM or to other balls).

NF – No function: When configured as a x4 device, these balls are NF. When configured

as a x8 device, these balls are defined as TDQS#, DQ[7:4].

8Gb: x8, x16 Automotive DDR3L SDRAM

Ball Assignments and Descriptions

09005aef861cf5fa

auto_8Gb_DDR3L.pdf - Rev. F 05/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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