5
4
3
2
1
D D
C C
B B
A
RSVD65_R
CFG0
CFG6
CFG7
RSVD_VSS
H_RSVD9_R
CFG15
CFG16
CFG14
CFG7
H_RSVD17_R
CFG1
CFG0
CFG3
CFG9
CFG10
CFG8
CFG17
H_RSVD18_R
CFG4
CFG2
H_RSVD10_R CFG3
RSVD64_R
CFG5
CFG4
CFG12
CFG13
CFG11
Title
Size Document Number Rev
Date: Sheet of
LA46 MB DIS
-1
10_CPU (7/7)-RESERVED
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
A3
10 58Tuesday, January 26, 2010
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
LA46 MB DIS
-1
10_CPU (7/7)-RESERVED
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
A3
10 58Tuesday, January 26, 2010
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
LA46 MB DIS
-1
10_CPU (7/7)-RESERVED
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
A3
10 58Tuesday, January 26, 2010
<Core Design>
VSS (AP34) can be left NC is
CRB implementation; EDS/DG
recommendation to GND.
PCI-Express Configuration Select
CFG0
1:Single PEG
0:Bifurcation enabled
CFG7(Reserved) - Temporarily used for early
Clarksfield samples.
CFG7 Clarksfield (only for early samples pre-ES1) -
Connect to GND with 3.01K Ohm/5% resistor.
Note: Only temporary for early CFD sample
(rPGA/BGA) [For details please refer to the
WW33 MoW and sighting report].
For a common M/B design (for AUB and CFD),
the pull-down resistor shouble be used. Does
not impact AUB functionality.
CFG3 - PCI-Express Static Lane Reversal
CFG3
1 :Normal Operation
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
CFG4 - Display Port Presence
CFG4
1:Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port
-1 0114
1
TP58TPAD14-GP TP58TPAD14-GP
1
TP57TPAD14-GP TP57TPAD14-GP
1 2
R231
0R0402-PAD
R231
0R0402-PAD
12
R235
3KR2F-GP
DY
R235
3KR2F-GP
DY
1
TP55TPAD14-GP TP55TPAD14-GP
1
TP52TPAD14-GP TP52TPAD14-GP
12
R233
3KR2F-GP
R233
3KR2F-GP
1
TP61TPAD14-GP TP61TPAD14-GP
1
TP62TPAD14-GP TP62TPAD14-GP
12
R234
3KR2F-GP
DY
R234
3KR2F-GP
DY
1
TP105TPAD14-GP TP105TPAD14-GP
1
TP36 TPAD14-GPTP36 TPAD14-GP
1
TP38TPAD14-GP TP38TPAD14-GP
1
TP56TPAD14-GP TP56TPAD14-GP
1
TP54TPAD14-GP TP54TPAD14-GP
1
TP51TPAD14-GP TP51TPAD14-GP
1
TP47TPAD14-GP TP47TPAD14-GP
CFG0
AM30
CFG1
AM28
CFG2
AP31
CFG3
AL32
CFG4
AL30
CFG5
AM31
CFG6
AN29
CFG7
AM32
CFG8
AK32
CFG9
AK31
CFG10
AK28
CFG11
AJ28
CFG12
AN30
CFG13
AN32
CFG14
AJ32
CFG15
AJ29
CFG16
AJ30
CFG17
AK30
RSVD#AH25
AH25
RSVD#AK26
AK26
RSVD#AJ26
AJ26
RSVD#AJ27
AJ27
RSVD_TP#H16
H16
RSVD#AL28
AL28
RSVD#AL29
AL29
RSVD#AP30
AP30
RSVD#AP32
AP32
RSVD#AL27
AL27
RSVD#AT31
AT31
RSVD#AT32
AT32
RSVD#AP33
AP33
RSVD#AR33
AR33
RSVD#AR32
AR32
RSVD#J28
J28
RSVD#J29
J29
RSVD#A19
A19
RSVD#B19
B19
RSVD#A20
A20
RSVD#B20
B20
RSVD#T9
T9
RSVD#U9
U9
RSVD#AB9
AB9
RSVD#AC9
AC9
RSVD_TP#AA5
AA5
RSVD_TP#AA4
AA4
RSVD_TP#R8
R8
RSVD_TP#AA2
AA2
RSVD_TP#AA1
AA1
RSVD_TP#R9
R9
RSVD_TP#AD3
AD3
RSVD_TP#AG7
AG7
RSVD_TP#AD2
AD2
RSVD_TP#AE3
AE3
RSVD_TP#V4
V4
RSVD_TP#V5
V5
RSVD_TP#N2
N2
RSVD_TP#W3
W3
RSVD_TP#W2
W2
RSVD_TP#N3
N3
RSVD_TP#AD5
AD5
RSVD_TP#AE5
AE5
RSVD_TP#AD7
AD7
RSVD_TP#AD9
AD9
RSVD#AL26
AL26
RSVD#AP25
AP25
RSVD#AL25
AL25
RSVD#AL24
AL24
RSVD#AL22
AL22
RSVD#AJ33
AJ33
RSVD#AG9
AG9
RSVD#M27
M27
RSVD#L28
L28
SA_DIMM_VREF#
J17
SB_DIMM_VREF#
H17
RSVD#G25
G25
RSVD#G17
G17
RSVD#E31
E31
RSVD#E30
E30
RSVD#AJ13
AJ13
RSVD#AJ12
AJ12
RSVD_TP#E15
E15
RSVD_TP#F15
F15
KEY
A2
RSVD#D15
D15
RSVD#C15
C15
RSVD#AJ15
AJ15
RSVD#AH15
AH15
VSS
AP34
RSVD_NCTF#AR2
AR2
RESERVED
5 OF 9
AUBURNDALE
CPU1E
AUBURUNF
RESERVED
5 OF 9
AUBURNDALE
CPU1E
AUBURUNF
1
TP48TPAD14-GP TP48TPAD14-GP
1
TP33 TPAD14-GPTP33 TPAD14-GP
1
TP49TPAD14-GP TP49TPAD14-GP
1
TP104TPAD14-GP TP104TPAD14-GP
12
R236
3KR2F-GP
DY
R236
3KR2F-GP
DY
1
TP59TPAD14-GP TP59TPAD14-GP
1
TP60TPAD14-GP TP60TPAD14-GP
1
TP37TPAD14-GP TP37TPAD14-GP