DDR3 SDRAM规格详解：MT41J系列

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"DDR3 datasheet提供了关于DDR3 SDRAM的详细规格和技术特性，主要讨论了Micron Technology生产的1Gb DDR3 SDRAM芯片，包括MT41J256M4、MT41J128M8和MT41J64M16等不同配置的内存芯片。这些芯片具有1.5V的工作电压，采用差分双向数据 strobe，8n位预取架构，以及多种CAS延迟选项。" DDR3 SDRAM是第三代动态随机存取存储器，相较于前代产品，它在速度、功耗和容量方面有所提升。在上述描述中，DDR3的主要特点如下： 1. **电压**：DDR3内存工作在VDD=VDDQ=+1.5V±0.075V的电压范围内，比DDR2的1.8V更低，有助于降低系统功耗。 2. **I/O接口**：使用1.5V中心终止的推挽式I/O，同时采用了差分双向数据 strobe（DQS），这种设计可以提高信号完整性和系统性能。 3. **预取架构**：DDR3 SDRAM采用8n位预取架构，意味着数据总线宽度是8位的8倍，提升了数据传输速率。 4. **时钟输入**：使用差分时钟输入（CK和CK#），可以减少时钟信号的噪声影响，提高系统时钟精度。 5. **内部银行**：拥有8个内部银行，使得多任务并行访问成为可能，提高了内存利用率和效率。 6. **CAS延迟**：提供了多种CAS（读取）延迟（CL）选项，包括5、6、7、8、9、10、11，以及POSTED CAS ADDITIVE latency (AL)和CAS（写入）延迟（CWL），这些参数可以根据系统的实际需求进行调整。 7. **突发长度**：固定突发长度（BL）为8，并支持通过模式寄存器集（MRS）进行4的突发切分（Burst Chop）。此外，还支持在运行过程中选择BL4或BL8的切换。 8. **自刷新模式**：具备自刷新功能，可以在系统待机时保持数据的完整性，且具有特定温度下的刷新周期要求。 9. **工作温度与刷新**：在0°C至95°C的温度范围内，DDR3内存有特定的刷新周期，例如64ms、8,192周期在0°C至85°C，32ms在85°C至95°C。 10. **时钟频率范围**：虽然描述中没有具体数值，但通常DDR3 SDRAM的工作频率可高达1066MHz甚至更高，这取决于具体的内存模块。 DDR3 SDRAM广泛应用于各种计算机系统，包括台式机、笔记本电脑、服务器和嵌入式系统，其高性能和低功耗特性使其成为现代电子设备中的主流内存类型。开发者在设计系统时，需要参考此类datasheet来确定内存模块的兼容性、性能参数以及系统设计要求。

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN

1Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

Figure 8: 96-Ball FBGA – x16 Ball Assignments (Top View)

Notes: 1. Ball descriptions listed in Table 5 on page 21 are listed as “x4, x8” if unique; otherwise, x4

and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

3. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to

the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined

in Table 5 on page 21).

1234 6 7895

VDDQ

SSQ

DDQ

SSQ

VDDQ

SSQ

REFDQ

ODT

VDD

VSS

VDD

VSS

DQ13

DQ11

DDQ

SSQ

DQ2

DQ6

DDQ

VDD

CS#

BA0

RESET#

DQ15

DQ9

UDM

DQ0

LDQS

LDQS#

DQ4

RAS#

CAS#

WE#

BA2

DQ12

UDQS#

UDQS

DQ8

LDM

DQ1

DQ7

CK#

A10/AP

A12/BC#

A11

VDDQ

DQ14

DQ10

SSQ

DQ3

DQ5

VDD

REFCA

BA1

VSS

VSSQ

DDQ

VDDQ

SSQ

DDQ

CKE

VDD

VSS

VDD

VSS

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN

1Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Ball Assignments Symbol Type Description

K3, L7, L3, K2,

L8, L2, M8, M2,

N8, M3, H7, M7,

K7, N3

A0, A1, A2, A3,

A4, A5, A6, A7,

A8, A9, A10/AP,

A11, A12/BC#,

A13

Input Address inputs: Provide the row address for ACTIVATE commands,

and the column address and auto precharge bit (A10) for READ/

WRITE commands, to select one location out of the memory array in

the respective bank. A10 sampled during a PRECHARGE command

determines whether the PRECHARGE applies to one bank (A10 LOW,

bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs

also provide the op-code during a LOAD MODE command. Address

inputs are referenced to V

REFCA. A12/BC#: When enabled in the

mode register (MR), A12 is sampled during READ and WRITE

commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop).

See Table 62 on page 91.

J2, K8, J3 BA0, BA1, BA2 Input Bank address inputs: BA[2:0] define the bank to which an

ACTIVATE, READ, WRITE, or PRECHARGE command is being applied.

BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is

loaded during the LOAD MODE command. BA[2:0] are referenced to

REFCA.

F7, G7 CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and

address input signals are sampled on the crossing of the positive

edge of CK and the negative edge of CK#. Output data strobe (DQS,

DQS#) is referenced to the crossings of CK and CK#.

G9 CKE Input Clock enable: CKE enables (registered HIGH) and disables

(registered LOW) internal circuitry and clocks on the DRAM. The

specific circuitry that is enabled/disabled is dependent upon the

DDR3 SDRAM configuration and operating mode. Taking CKE LOW

provides PRECHARGE power-down and SELF REFRESH operations (all

banks idle), or active power-down (row active in any bank). CKE is

synchronous for power-down entry and exit and for self refresh

entry. CKE is asynchronous for self refresh exit. Input buffers

(excluding CK, CK#, CKE, RESET#, and ODT) are disabled during

power-down. Input buffers (excluding CKE and RESET#) are disabled

during SELF REFRESH. CKE is referenced to V

REFCA.

H2 CS# Input Chip select: CS# enables (registered LOW) and disables (registered

HIGH) the command decoder. All commands are masked when CS# is

registered HIGH. CS# provides for external rank selection on systems

with multiple ranks. CS# is considered part of the command code.

CS# is referenced to V

REFCA.

B7 DM Input Input data mask: DM is an input mask signal for write data. Input

data is masked when DM is sampled HIGH along with the input data

during a write access. Although the DM ball is input-only, the DM

loading is designed to match that of the DQ and DQS balls. DM is

referenced to V

REFDQ. DM has an optional use as TDQS on the x8.

G1 ODT Input On-die termination: ODT enables (registered HIGH) and disables

(registered LOW) termination resistance internal to the DDR3

SDRAM. When enabled in normal operation, ODT is only applied to

each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8;

DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if

disabled via the LOAD MODE command. ODT is referenced to

REFCA.

F3, G3, H3 RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define

the command being entered and are referenced to V

REFCA.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN

1Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

N2 RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The

RESET# input receiver is a CMOS input defined as a rail-to-rail signal

with DC HIGH ≥ 0.8 × V

DDQ and DC LOW ≤ 0.2 × VDDQ. RESET#

assertion and desertion are asynchronous.

B3, C7,

C2, C8

DQ0, DQ1,

DQ2, DQ3

I/O Data input/output: Bidirectional data bus for the x4 configuration.

DQ[3:0] are referenced to VREFDQ.

B3, C7, C2,

C8, E3, E8,

D2, E7

DQ0, DQ1, DQ2,

DQ3, DQ4, DQ5,

DQ6, DQ7

I/O Data input/output: Bidirectional data bus for the x8 configuration.

DQ[7:0] are referenced to VREFDQ.

C3, D3 DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data.

Input with write data. Center-aligned to write data.

B7, A7 TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only.

When TDQS is enabled, DM is disabled, and the TDQS and TDQS#

balls provide termination resistance.

A2, A9, D7, G2, G8,

K1, K9, M1, M9

DD Supply Power supply: 1.5V ±0.075V.

B9, C1, E2, E9 VDDQ Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for

improved noise immunity.

J8 V

REFCA Supply Reference voltage for control, command, and address: VREFCA

must be maintained at all times (including self refresh) for proper

device operation.

E1 VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all

times (including self refresh) for proper device operation.

A1, A8, B1, D8, F2,

F8, J1, J9, L1, L9, N1,

VSS Supply Ground.

B2, B8, C9, D1, D9 VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.

H8 ZQ Reference External reference ball for output drive calibration: This ball is

tied to an external 240Ω resistor (RZQ), which is tied to VSSQ.

A3, J7, N7, F9, H1, F1,

NC – No connect: These balls should be left unconnected (the ball has no

connection to the DRAM or to other balls).

A7, D2, E3, E7, E8 NF – No function: When configured as a x4 device, these balls are NF.

When configured as a x8 device, these balls are defined as TDQS#,

DQ[7:4].

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (continued)

Ball Assignments Symbol Type Description

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN

1Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

Table 4: 86-Ball FBGA – x4, x8 Ball Descriptions

Ball Assignments Symbol Type Description

N3, P7, P3, N2,

P8, P2, R8, R2,

T8, R3,

L7,

R7, N7,

A0, A1, A2, A3,

A4, A5, A6, A7,

A8, A9

A10/AP,

A11, A12/BC#,

A13

Input Address inputs: Provide the row address for ACTIVATE commands,

and the column address and auto precharge bit (A10) for READ/

WRITE commands, to select one location out of the memory array in

the respective bank. A10 sampled during a PRECHARGE command

determines whether the PRECHARGE applies to one bank (A10 LOW,

bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs

also provide the op-code during a LOAD MODE command. Address

inputs are referenced to V

REFCA. A12/BC#: When enabled in the

mode register (MR), A12 is sampled during READ and WRITE

commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop).

See Table 62 on page 91.

M2, N8, M3 BA0, BA1, BA2 Input Bank address inputs: BA[2:0] define the bank to which an

ACTIVATE, READ, WRITE, or PRECHARGE command is being applied.

BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is

loaded during the LOAD MODE command. BA[2:0] are referenced to

REFCA.

J7, K7 CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and

address input signals are sampled on the crossing of the positive

edge of CK and the negative edge of CK#. Output data strobe (DQS,

DQS#) is referenced to the crossings of CK and CK#.

K9 CKE Input Clock enable: CKE enables (registered HIGH) and disables

(registered LOW) internal circuitry and clocks on the DRAM. The

specific circuitry that is enabled/disabled is dependent upon the

DDR3 SDRAM configuration and operating mode. Taking CKE LOW

provides PRECHARGE power-down and SELF REFRESH operations (all

banks idle), or active power-down (row active in any bank). CKE is

synchronous for power-down entry and exit and for self refresh

entry. CKE is asynchronous for self refresh exit. Input buffers

(excluding CK, CK#, CKE, RESET#, and ODT) are disabled during

power-down. Input buffers (excluding CKE and RESET#) are disabled

during SELF REFRESH. CKE is referenced to V

REFCA.

L2 CS# Input Chip select: CS# enables (registered LOW) and disables (registered

HIGH) the command decoder. All commands are masked when CS# is

registered HIGH. CS# provides for external rank selection on systems

with multiple ranks. CS# is considered part of the command code.

CS# is referenced to V

REFCA.

E7 DM Input Input data mask: DM is an input mask signal for write data. Input

data is masked when DM is sampled HIGH along with the input data

during a write access. Although the DM ball is input-only, the DM

loading is designed to match that of the DQ and DQS balls. DM is

referenced to V

REFDQ. DM has an optional use as TDQS on the x8.

K1 ODT Input On-die termination: ODT enables (registered HIGH) and disables

(registered LOW) termination resistance internal to the DDR3

SDRAM. When enabled in normal operation, ODT is only applied to

each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8;

DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if

disabled via the LOAD MODE command. ODT is referenced to

REFCA.

J3, K3, L3 RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define

the command being entered and are referenced to V

REFCA.

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice.

1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN

1Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

T2 RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The

RESET# input receiver is a CMOS input defined as a rail-to-rail signal

with DC HIGH ≥ 0.8 × V

DDQ and DC LOW ≤ 0.2 × VDDQ. RESET#

assertion and desertion are asynchronous.

E3, F7,

F2, F8

DQ0, DQ1,

DQ2, DQ3

I/O Data input/output: Bidirectional data bus for the x4 configuration.

DQ[3:0] are referenced to VREFDQ.

E3, F7, F2,

F8, H3, H8,

G2, H7

DQ0, DQ1, DQ2,

DQ3, DQ4, DQ5,

DQ6, DQ7

I/O Data input/output: Bidirectional data bus for the x8 configuration.

DQ[7:0] are referenced to VREFDQ.

F3, G3 DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data.

Input with write data. Center-aligned to write data.

E7, D7 TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only.

When TDQS is enabled, DM is disabled, and the TDQS and TDQS#

balls provide termination resistance.

D2, D9, G7, K2, K8,

N1, N9, R1, R9

DD Supply Power supply: 1.5V ±0.075V.

E9, F1, H2, H9 VDDQ Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for

improved noise immunity.

M8 V

REFCA Supply Reference voltage for control, command, and address: VREFCA

must be maintained at all times (including self refresh) for proper

device operation.

H1 VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all

times (including self refresh) for proper device operation.

D1, D8, E1, G8, J2, J8,

M1, M9, P1, P9, T1,

VSS Supply Ground.

E2, E8, F9, G1, G9 VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.

L8 ZQ Reference External reference ball for output drive calibration: This ball is

tied to an external 240Ω resistor (RZQ), which is tied to VSSQ.

A1, A3, A7, A9, D3,

J1, J9, L1, L9, M7, T7,

W1, W3, W7, W9

NC – No connect: These balls should be left unconnected (the ball has no

connection to the DRAM or to other balls).

D7, G2, H3, H7, H8 NF – No function: When configured as a x4 device, these balls are NF.

When configured as a x8 device, these balls are defined as TDQS#,

DQ[7:4].

Table 4: 86-Ball FBGA – x4, x8 Ball Descriptions (continued)

Ball Assignments Symbol Type Description

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