TI TLK1211：0.25μm工艺的1.25-1.3Gbps以太网串行器

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TI-TLK1211是一款基于先进的0.25微米CMOS工艺设计的以太网串行器，旨在提供高效、低功耗和全面的特性。该产品的主要亮点包括： 1. 高速数据传输：支持从0.6 Gbps到1.3 Gbps的速率，满足不同应用场景的需求，适用于高带宽通信。 2. 内置测试功能：集成了一套全面的内置测试功能，方便设备的生产和维护过程中的故障诊断与性能验证。 3. 低功耗设计：在1.25 Gbps工作状态下，典型的功耗仅为250毫瓦，这对于能源效率和系统整体成本控制具有显著优势。 4. 标准兼容性：采用LVPECL兼容的差分输入输出接口，对于高电压环境有良好的适应性，并且支持3.3伏LVTTL输入，增强了灵活性。 5. JTAG支持：集成IEEE 1149.1 JTAG接口，便于硬件调试和升级，提高了开发效率。 6. 快速重锁时间：小于256纳秒的典型重锁时间，确保了数据传输的稳定性和可靠性。 7. 电源选择：提供2.5伏电源选项，特别适合对功率消耗敏感的EPON/GEPON（无源光网络）应用，降低了系统复杂性和成本。 8. 易于使用：无需外部滤波电容器，简化了电路设计和组装过程。 9. 样品获取：通过TI官网可以查询并申请样品，以便于评估和集成到实际项目中。 TI-TLK1211是一款针对高速以太网应用的理想解决方案，它集成了高性能、低功耗和高度可测试的特点，为设计者提供了简化的设计流程和可靠的通信保障。在选择以太网串行器时，这款产品无疑是值得考虑的优质选择。

TLK1211RCP

www.ti.com

SLLS658D – SEPTEMBER 2006– REVISED APRIL 2011

Terminal Functions (continued)

TERMINAL

I/O DESCRIPTION

NAME NO.

LOOPEN 19 I Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The

P/D

(3)

transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test

capability in conjunction with the protocol device. The TXP and TXN outputs are held in a

high-impedance state during the loop-back test. LOOPEN is held low during standard operational

state with external serial outputs and inputs active.

PRBSEN 16 I PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS

P/D

(3)

verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive

inputs and checked for errors, that are reported by the SYNC/PASS terminal indicating low.

TCK 49 I Test clock. IEEE1149.1 (JTAG)

TESTEN 17 I Manufacturing test terminal

P/D

(3)

POWER

VDD 5, 10, Supply Digital logic power. Provides power for all digital circuitry and digital I/O buffers.

20, 23,

29, 37,

42, 50,

VDDA 53, 57, Supply Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter

59, 60

VDDPLL 18 Supply PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.

GROUND

GND 1, 14, Ground Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.

21,25,

33, 46

GNDA 51, 58 Ground Analog ground. GNDA provides a ground for the high-speed analog circuits RX and TX.

GNDPLL 64 Ground PLL ground. Provides a ground for the PLL circuitry.

(3) P/D = Internal pulldown

DETAILED DESCRIPTION

Data Transmission

This device supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing DDR clocking.

When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is selected.

In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data,

TD0–TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock

by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted

sequentially bits 0 through 9 over the differential high-speed I/O channel.

In the DDR mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins TD0–TD4. In this mode, data

is aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and

sent to the serializer. The rising edge REFCLK clocks in bits 0–4, and the falling edge of REFCLK clocks in bits

5–9. Bit 0 is the first bit transmitted.

Transmission Latency

Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of bit

9. The minimum latency in TBI mode is 20 bit times. The maximum latency in TBI mode is 22 bit times. The

minimum latency in DDR mode is 30 bit times, and maximum latency in DDR mode is 32 bit times.

Product Folder Link(s): TLK1211RCP

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