Atmega128A：高性能8位微控制器详细数据手册

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Atmega128A是一款高性能、低功耗的AVR 8位微控制器，它基于先进的RISC架构设计，旨在提供高效能与灵活性。这款微控制器的特点包括： 1. **强大的指令集**：Atmega128A拥有133条强大指令，大部分操作可在单个时钟周期内完成，这显著提高了处理速度和程序效率。 2. **丰富的寄存器**：内置32个8位通用工作寄存器和外围控制寄存器，使得数据处理和外设管理更加高效。所有操作支持全静态操作模式，即使在功耗敏感的应用中也能保持高效运行。 3. **内存容量与耐久性**：它具有128KB的自编程闪存，用于长期存储程序代码，支持高达16MIPS的执行性能（在16MHz时钟下）。非易失性存储还包括4KB的EEPROM用于存储数据，以及4KB的内部SRAM。这些存储单元具有高耐用性，如在85°C下的Flash写/擦除循环可达10,000次，而EEPROM则为100,000次。数据在无需电源的情况下可以保持长达20年（85°C）或100年（25°C）的持久性。 4. **可选功能**：提供了独立的Boot Code区域，并支持内部Boot Program进行在系统编程(ISP)，允许程序在运行时进行更新。此外，Atmega128A支持真正的读写同时操作，这在需要频繁读取和修改程序的场合非常有用。 5. **扩展内存**：最大可支持64KB的外部内存空间，增加了系统的存储能力。同时，为了增强软件安全性，还提供编程锁定功能。 6. **通信接口**：内置SPI接口，便于在系统编程，方便与其他设备通信。此外，它还具备JTAG（IEEE 1149.1标准兼容）接口，支持边界扫描测试、全面的芯片级调试，以及通过JTAG对闪存、EEPROM、熔丝和锁定位进行编程。 7. **外围设备支持**：两个独立的8位定时器/计数器，每个都有单独的预分频器，可满足各种时间测量和计数应用的需求。 Atmega128A凭借其高效的处理器性能、丰富的内存选项、安全的编程机制和多种接口，成为工业控制、嵌入式系统和物联网应用的理想选择。开发人员可以根据具体需求利用这些特性来设计出高效且可靠的解决方案。

8151E–AVR–02/10

ATmega128A

in order to execute the interrupt handling routine, and hardware clears the corresponding inter-

rupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be

cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared,

the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared

by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable

bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global

interrupt enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These

interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the

interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one

more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor

restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

CLI instruction. The following example shows how this can be used to avoid interrupts during the

timed EEPROM write sequence.

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in this example.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

8151E–AVR–02/10

ATmega128A

7.2 SRAM Data Memory

The ATmega128A supports two different configurations for the SRAM data memory as listed in

Table 7-1.

Figure 7-2 shows how the ATmega128A SRAM Memory is organized.

The ATmega128A is a complex microcontroller with more peripheral units than can be sup-

ported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the

Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc-

tions can be used. The Extended I/O space does not exist when the ATmega128A is in the

ATmega103 compatibility mode.

In normal mode, the first 4352 Data Memory locations address both the Register file, the I/O

Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the

memory, and the next 4096 locations address the internal data SRAM.

In ATmega103 compatibility mode, the first 4096 Data Memory locations address both the Reg-

ister file, the I/O Memory and the internal data SRAM. The first 32 locations address the Register

file, the next 64 location the standard I/O memory, and the next 4000 locations address the inter-

nal data SRAM.

An optional external data SRAM can be used with the ATmega128A. This SRAM will occupy an

area in the remaining address locations in the 64K address space. This area starts at the

address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM

occupies the lowest 4352 bytes in normal mode, and the lowest 4096 bytes in the ATmega103

compatibility mode (Extended I/O not present), so when using 64KB (65536 bytes) of External

Memory, 61184 Bytes of External Memory are available in normal mode, and 61440 Bytes in

ATmega103 compatibility mode. See “External Memory Interface” on page 22 for details on how

to take advantage of the external memory map.

When the addresses accessing the SRAM memory space exceeds the internal data memory

locations, the external data SRAM is accessed using the same instructions as for the internal

data memory access. When the internal data memories are accessed, the read and write strobe

pins (PG0

and PG1) are inactive during the whole access cycle. External SRAM operation is

enabled by setting the SRE bit in the MCUCR Register.

Accessing external SRAM takes one additional clock cycle per byte compared to access of the

internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP

take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine

calls and returns take three clock cycles extra because the two-byte program counter is pushed

and popped, and external memory access does not take advantage of the internal pipe-line

memory access. When external SRAM interface is used with wait-state, one-byte external

access takes two, three, or four additional clock cycles for one, two, and three wait-states

respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles

more than specified in the instruction set manual for one, two, and three wait-states.

Table 7-1. Memory Configurations

Configuration Internal SRAM Data Memory External SRAM Data Memory

Normal mode 4096 up to 64K

ATmega103 Compatibility

mode

4000 up to 64K

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