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Intel PXA27x处理器家族开发者手册
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更新于2024-08-02
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本资源是Intel PXA27x处理器家族开发者手册,发布于2006年1月。Intel PXA27x系列是专为嵌入式系统和移动设备设计的高性能处理器,旨在提供高效能和低功耗的解决方案。手册详尽介绍了该处理器的技术规格、架构特性以及开发者的使用指南。
主要内容涵盖了以下几个方面:
1. 处理器概述:文档首先定义了PXA27x处理器的基本信息,包括其在Intel产品线中的位置,强调了其在诸如手持设备、工业控制、消费电子等领域的应用潜力。
2. 技术规格:手册提供了处理器的详细规格,包括处理器核心频率、处理能力、内存支持、接口速度等关键性能参数,帮助开发者理解其硬件性能和兼容性要求。
3. 架构与特性:文档深入解析了PXA27x的体系结构,包括指令集、CPU核心设计、图形处理单元(GPU)功能,以及与之相关的硬件加速特性,如多媒体引擎和无线通信模块。
4. 编程接口:手册还介绍了开发工具包和软件开发接口(SDK),以便开发者能够有效地利用处理器的特性进行应用程序开发,包括驱动程序编写、操作系统集成和应用编程接口的使用。
5. 安全性和可靠性:强调了PXA27x在医疗、生命维持、安全控制和核设施等高风险环境下的局限性,以及Intel对其产品的责任声明,表明产品并不适合这类严格的安全标准应用。
6. 法律声明与许可:手册的法律部分明确了Intel对于文档和产品提供的使用条款,包括销售条件、保修政策,以及关于专利、版权和知识产权的声明,提醒开发者在使用时需遵守相关规定。
7. 许可限制:Intel可能拥有与PXA27x相关的专利或申请,提供文档和信息并不代表授予任何形式的专利许可,开发者在使用过程中应尊重并避免侵犯这些知识产权。
这本手册是Intel PXA27x处理器开发者的必备参考资料,它不仅提供了硬件技术细节,还为软件开发者提供了一套完整的开发框架和注意事项,确保用户在使用过程中遵循最佳实践和法律法规。
xvi Intel
®
PXA27x Processor Family Developer’s Manual
Contents
21 Real-Time Clock (RTC) ..............................................................................................................21-1
21.1 Overview..........................................................................................................................21-1
21.2 Features...........................................................................................................................21-1
21.3 Signal Descriptions..........................................................................................................21-2
21.4 Operation .........................................................................................................................21-2
21.4.1 Timer...................................................................................................................21-5
21.4.2 Wristwatch ..........................................................................................................21-5
21.4.3 Stopwatch.........................................................................................................21-10
21.4.4 Periodic Interrupt ..............................................................................................21-11
21.4.5 Trimmer ............................................................................................................21-12
21.4.6 Low-Power Modes ............................................................................................21-15
21.5 Register Descriptions.....................................................................................................21-15
21.5.1 RTC Trim Register (RTTR)...............................................................................21-16
21.5.2 RTC Status Register (RTSR)............................................................................21-17
21.5.3 RTC Alarm Register (RTAR) ............................................................................21-19
21.5.4 RTC Wristwatch Day Alarm Registers (RDARx) ..............................................21-20
21.5.5 RTC Wristwatch Year Alarm Registers (RYARx) .............................................21-21
21.5.6 RTC Stopwatch Alarm Registers (SWARx)......................................................21-22
21.5.7 RTC Periodic Interrupt Alarm Register (PIAR) .................................................21-23
21.5.8 RTC Counter Register (RCNR) ........................................................................21-24
21.5.9 RTC Day Counter Register (RDCR) .................................................................21-24
21.5.10 RTC Year Counter Register (RYCR)................................................................21-25
21.5.11 RTC Stopwatch Counter Register (SWCR) ......................................................21-26
21.5.12 RTC Periodic Interrupt Counter Register (RTCPICR) ......................................21-26
21.6 Register Summary.........................................................................................................21-27
22 Operating System Timers...........................................................................................................22-1
22.1 Overview..........................................................................................................................22-1
22.2 Features...........................................................................................................................22-1
22.3 Signal Descriptions..........................................................................................................22-2
22.4 Operation .........................................................................................................................22-2
22.4.1 Block Diagrams...................................................................................................22-2
22.4.2 Compares and Matches......................................................................................22-4
22.4.3 PXA25x Processor Compatibility........................................................................22-5
22.4.4 Timer Channels ..................................................................................................22-5
22.4.5 Counter Resolutions ...........................................................................................22-5
22.4.6 External Synchronization (EXT_SYNC<1:0>) ....................................................22-6
22.4.7 Output Generation ..............................................................................................22-7
22.4.8 Snapshot Mode...................................................................................................22-8
22.4.9 Operation in Low-Power Modes .........................................................................22-8
22.5 Register Descriptions.......................................................................................................22-9
22.5.1 OS Match Control Registers (OMCRx)...............................................................22-9
22.5.2 OS Timer Match Registers (OSMRx) ...............................................................22-14
22.5.3 OS Timer Watchdog Match Enable Register (OWER) .....................................22-15
22.5.4 OS Timer Interrupt Enable Register (OIER) .....................................................22-16
22.5.5 OS Timer Count Register 0 (OSCR0)...............................................................22-16
22.5.6 OS Timer Count Registers (OSCR4–11)..........................................................22-17
22.5.7 OS Timer Status Register (OSSR) ...................................................................22-17
22.5.8 OS Timer Snapshot Register (OSNR)..............................................................22-18
22.6 Register Summary.........................................................................................................22-19
Intel
®
PXA27x Processor Family Developer’s Manual xvii
Contents
23 Pulse Width Modulator Controller...............................................................................................23-1
23.1 Overview..........................................................................................................................23-1
23.2 Features...........................................................................................................................23-1
23.3 Signal Descriptions ..........................................................................................................23-2
23.4 Operation .........................................................................................................................23-2
23.4.1 Block Diagram ....................................................................................................23-4
23.4.2 Interdependencies ..............................................................................................23-4
23.4.3 Reset Sequence .................................................................................................23-4
23.4.4 Programming Considerations .............................................................................23-5
23.4.5 Power Management............................................................................................23-6
23.5 Register Descriptions.......................................................................................................23-7
23.5.1 PWM Control Registers (PWMCRx) ...................................................................23-7
23.5.2 PWM Duty Cycle Registers (PWMDCRx)...........................................................23-8
23.5.3 PWM Period Control Registers (PWMPCRx) .....................................................23-9
23.6 Register Summary .........................................................................................................23-10
24 General-Purpose I/O Controller..................................................................................................24-1
24.1 Overview..........................................................................................................................24-1
24.2 Features...........................................................................................................................24-1
24.3 Signal Descriptions ..........................................................................................................24-1
24.4 Operation .........................................................................................................................24-2
24.4.1 GPIO Operation as Application-Specific GPIO ...................................................24-2
24.4.2 GPIO Operation as Alternate Function ...............................................................24-3
24.5 Register Descriptions.....................................................................................................24-10
24.5.1 GPIO Pin-Direction Registers (GPDR) .............................................................24-11
24.5.2 GPIO Pin-Output Set Registers (GPSR) and GPIO Pin-Output
Clear Registers (GPCR) ................................................................................................24-14
24.5.3 GPIO Rising-Edge Detect Enable Registers (GRER0/1/2/3) and
Falling-Edge Detect Enable Registers (GFER0/1/2/3) ..................................................24-18
24.5.4 GPIO Alternate Function Register (GAFR).......................................................24-23
24.5.5 GPIO Pin-Level Registers (GPLRx)..................................................................24-28
24.5.6 GPIO Edge Detect Status Register (GEDR).....................................................24-30
24.6 Register Summary .........................................................................................................24-33
25 Interrupt Controller......................................................................................................................25-1
25.1 Overview..........................................................................................................................25-1
25.2 Features...........................................................................................................................25-1
25.3 Signal Descriptions ..........................................................................................................25-2
25.4 Operation .........................................................................................................................25-2
25.4.1 Accessing Interrupt Controller Registers ............................................................25-4
25.4.2 Enabling and Accessing the Coprocessor ..........................................................25-4
25.4.3 Bit Positions and Peripheral IDs .........................................................................25-5
25.5 Register Descriptions.......................................................................................................25-6
25.5.1 Interrupt Controller Pending Registers (ICPR and ICPR2).................................25-6
25.5.2 Interrupt Controller IRQ Pending Registers (ICIP and ICIP2)...........................25-10
25.5.3 Interrupt Controller FIQ Pending Registers (ICFP and ICFP2).........................25-15
25.5.4 Interrupt Controller Mask Registers (ICMR and ICMR2) ..................................25-19
25.5.5 Interrupt Controller Level Registers (ICLR and ICLR2) ....................................25-23
25.5.6 Interrupt Controller Control Register (ICCR).....................................................25-27
25.5.7 Interrupt Priority Registers 0–39 (IPRx)............................................................25-28
xviii Intel
®
PXA27x Processor Family Developer’s Manual
Contents
25.5.8 Interrupt Control Highest Priority Register (ICHP) ............................................25-29
25.6 Register Summary.........................................................................................................25-31
26 Software Debug..........................................................................................................................26-1
26.1 Overview..........................................................................................................................26-1
26.2 Features...........................................................................................................................26-1
26.3 Signal Descriptions..........................................................................................................26-1
26.4 Operation .........................................................................................................................26-2
26.4.1 Debug Exceptions...............................................................................................26-2
26.4.2 Hardware Breakpoint Resources........................................................................26-5
26.4.3 Software Breakpoints..........................................................................................26-7
26.4.4 Normal RX Handshaking versus High-Speed Download....................................26-7
26.4.5 Executing Conditionally Using TXRXCTRL ........................................................26-8
26.4.6 Debug JTAG Access ..........................................................................................26-8
26.4.7 Trace Buffer......................................................................................................26-24
26.4.8 Halt Mode Software Protocol............................................................................26-29
26.4.9 Software Debug Notes......................................................................................26-35
26.5 Register Descriptions.....................................................................................................26-36
26.5.1 Transmit/Receive Control Register (TXRXCTRL) ............................................26-36
26.5.2 Debug Control and Status Register (DCSR) ....................................................26-38
26.5.3 Data Breakpoint Controls Register (DBCON)...................................................26-41
26.5.4 Instruction Breakpoint Address and Control Register (IBCRx).........................26-42
26.5.5 Data Breakpoint Register (DBRx).....................................................................26-43
26.5.6 Transmit Register (TX) .....................................................................................26-43
26.5.7 Receive Register (RX)......................................................................................26-44
26.5.8 Checkpoint Registers (CHKPTx) ......................................................................26-44
26.5.9 Trace Buffer Register (TBREG)........................................................................26-45
26.6 Register Summary.........................................................................................................26-46
27 Quick Capture Interface..............................................................................................................27-1
27.1 Overview..........................................................................................................................27-1
27.2 Features...........................................................................................................................27-1
27.3 Signal Descriptions..........................................................................................................27-2
27.4 Operation .........................................................................................................................27-2
27.4.1 Operating Modes ................................................................................................27-3
27.4.2 Clock (CICLK and MCLK) Generation................................................................27-9
27.4.3 Serial-to-Parallel Conversion ..............................................................................27-9
27.4.4 FIFO Operation.................................................................................................27-10
27.4.5 Pixel Formats....................................................................................................27-12
27.4.6 Functional Timing .............................................................................................27-21
27.5 Register Descriptions.....................................................................................................27-24
27.5.1 Quick Capture Interface Control Register 0 (CICR0)........................................27-24
27.5.2 Quick Capture Interface Control Register 1 (CICR1)........................................27-28
27.5.3 Quick Capture Interface Control Register 2 (CICR2)........................................27-32
27.5.4 Quick Capture Interface Control Register 3 (CICR3)........................................27-33
27.5.5 Quick Capture Interface Control Register 4 (CICR4)........................................27-34
27.5.6 Quick Capture Interface Time-Out Register (CITOR).......................................27-37
27.5.7 Quick Capture Interface Status Register (CISR) ..............................................27-37
27.5.8 Quick Capture Interface FIFO Control Register (CIFR)....................................27-40
27.5.9 Quick Capture Interface Receive Buffer Registers (CIBRx) .............................27-42
Intel
®
PXA27x Processor Family Developer’s Manual xix
Contents
27.6 Register Summary .........................................................................................................27-43
28 Memory Map and Registers .......................................................................................................28-1
28.1 Overview..........................................................................................................................28-1
28.2 System Bus Unit Registers ..............................................................................................28-4
28.2.1 Intel XScale
®
Microarchitecture Core Registers .................................................28-4
28.2.2 Memory Controller Registers ..............................................................................28-6
28.2.3 LCD Controller Registers....................................................................................28-7
28.2.4 USB Host Controller Registers ...........................................................................28-9
28.2.5 Internal Memory Registers................................................................................28-10
28.2.6 Quick Capture Interface Registers....................................................................28-11
28.3 Peripheral Module Registers .........................................................................................28-12
29 System Bus Arbiter.....................................................................................................................29-1
29.1 Overview..........................................................................................................................29-1
29.2 Features...........................................................................................................................29-1
29.3 Signal Descriptions ..........................................................................................................29-1
29.4 Operation .........................................................................................................................29-1
29.4.1 Programmable Weights ......................................................................................29-1
29.4.2 Bus Parking ........................................................................................................29-2
29.5 Register Descriptions.......................................................................................................29-2
29.5.1 Arbiter Control Register (ARB_CNTRL)..............................................................29-2
29.6 System Considerations....................................................................................................29-3
29.6.1 Access Latency on System Bus .........................................................................29-3
29.6.2 I/O Ordering ........................................................................................................29-4
29.6.3 Flushing the Memory Controller Buffers .............................................................29-4
29.6.4 Semaphores .......................................................................................................29-5
29.6.5 Interrupts.............................................................................................................29-5
29.7 Register Summary ...........................................................................................................29-5
Glossary..................................................................................................................................... Glossary-1
Index ...............................................................................................................................................Index-1
xx Intel
®
PXA27x Processor Family Developer’s Manual
Contents
Figures:
1-1 Intel
®
PXA27x Processor Block Diagram for a Typical System ............................................1-5
3-1 Clocks Manager and Clocks Distribution Block Diagram ....................................................3-15
3-2 Power Manager and Internal Power Domain Block Diagram ..............................................3-36
3-3 Overview of Power Manager Modes of Operation ..............................................................3-37
3-4 Typical System Diagram .....................................................................................................3-52
3-5 Initial Power-On and Deep-Sleep Exit States......................................................................3-53
4-1 Internal Memory Block Diagram............................................................................................4-2
5-1 DMA Controller Block Diagram .............................................................................................5-3
5-2 DREQ Timing Requirements.................................................................................................5-3
5-3 Descriptor-Fetch Transfer Channel State Diagram...............................................................5-8
5-4 Flow Chart for Descriptor Branching .....................................................................................5-9
5-5 No-Descriptor-Fetch Transfer Channel State Diagram .......................................................5-10
5-6 Fly-By Transfer Diagram .....................................................................................................5-17
5-7 Real-Time Fly-By DMA Operation for SDRAM....................................................................5-18
5-8 Descriptor Chain for Software Implementation of Full and Empty Bits................................5-30
5-9 Descriptor Behavior on End-of-Receive (EOR)...................................................................5-47
6-1 General Memory Interface Configuration ..............................................................................6-5
6-2 Programmable SDRAM Memory Map Options .....................................................................6-7
6-3 External-to-Internal Address Mapping Options .....................................................................6-9
6-4 SDRAM Power-On State Machine ......................................................................................6-22
6-5 Variable-Latency I/O Diagram .............................................................................................6-28
6-6 PC Card Memory Map.........................................................................................................6-30
6-7 Alternate Bus-Master Mode.................................................................................................6-36
6-8 Alternate Bus Master Refresh Options................................................................................6-37
6-9 SDRAM Memory System Example .....................................................................................6-38
6-10 Static Memory System Example .........................................................................................6-39
6-11 Programmable Static Memory Map Options .......................................................................6-70
6-12 Addressing Instructions for Static Memory Chip Selects.....................................................6-70
7-1 LCD Controller Block Diagram ..............................................................................................7-4
7-2 Temporal Dithering Concept .................................................................................................7-6
7-3 Compare Range for TMED....................................................................................................7-7
7-4 TMED Block Diagram............................................................................................................7-8
7-5 Hardware Cursor, Base Plus 2 Overlays Displayed on LCD Panel ....................................7-12
7-6 Luminance and Chrominance Samples in 4:4:4 YCbCr Video Frame ................................7-20
7-7 Luminance and Chrominance Samples in 4:2:2 Video Frame ............................................7-21
7-8 Luminance and Chrominance Samples in 4:2:0 YCbCr Video Frame ................................7-21
7-9 Overlay 1 Frame Buffer Format...........................................................................................7-23
7-10 Overlay 2 Frame Buffer Format for 4:4:4 YCbCr Packed Format .......................................7-25
7-11 Overlay 2 Frame Buffer Format for YCbCr Planar Format..................................................7-25
7-12 Bilinear Interpolation for 1/2X, 1/2Y, and 1/2XY Locations .................................................7-26
7-13 2:1 Upsampling in the Horizontal Dimension .....................................................................7-26
7-14 2:1 Upsampling in the Horizontal and Vertical Dimensions................................................7-27
7-15 Interface to LCD Smart Panel with Internal Frame Buffer ..................................................7-29
7-16 Cursor Position within Display Frame .................................................................................7-33
7-17 Palette Data Formats—Transparency Disabled..................................................................7-34
7-18 Palette Data Formats 0b01—Transparency Enabled..........................................................7-34
7-19 Palette Data Formats 0b10—Transparency Enabled..........................................................7-34
7-20 Palette Data Formats 0b11—Transparency Enabled..........................................................7-35
7-21 Format for Palette Data.......................................................................................................7-36
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