make uart Verilog HDL program

As an AI language model, I cannot write a Verilog HDL program. However, I can provide you with an example UART Verilog HDL program that you can use as a reference to write your own program.

// UART Verilog HDL Program
module uart (
input clk,
input resetn,
input rx,
output tx
);

parameter BAUD_RATE = 9600;
parameter CLK_FREQ = 50000000;

reg [7:0] data_in;
reg [7:0] data_out;
reg [3:0] bit_count;
reg [3:0] baud_count;
reg [3:0] state;

assign tx = state[0];

always @(posedge clk or negedge resetn) begin
if (~resetn) begin
data_in <= 8'h00;
data_out <= 8'h00;
bit_count <= 4'h0;
baud_count <= 4'h0;
state <= 4'h0;
end else begin
case (state)
// Idle state
4'h0: begin
if (~rx) begin
state <= 4'h1;
bit_count <= 4'h0;
baud_count <= 4'h0;
end
end
// Start bit state
4'h1: begin