格雷码转二进制的verilog程序及其testbench文件编写

以下是格雷码转二进制的Verilog程序及其testbench文件编写：

Verilog程序：

module gray_to_binary(
    input wire [3:0] gray,
    output reg [3:0] binary
);

always @ (gray) begin
    case (gray)
        4'b0000: binary = 4'b0000;
        4'b0001: binary = 4'b0001;
        4'b0011: binary = 4'b0010;
        4'b0010: binary = 4'b0011;
        4'b0110: binary = 4'b0100;
        4'b0111: binary = 4'b0101;
        4'b0101: binary = 4'b0110;
        4'b0100: binary = 4'b0111;
        4'b1100: binary = 4'b1000;
        4'b1101: binary = 4'b1001;
        4'b1111: binary = 4'b1010;
        4'b1110: binary = 4'b1011;
        4'b1010: binary = 4'b1100;
        4'b1011: binary = 4'b1101;
        4'b1001: binary = 4'b1110;
        4'b1000: binary = 4'b1111;
    endcase
end

endmodule

testbench文件：

module gray_to_binary_tb();

reg [3:0] gray;
wire [3:0] binary;

gray_to_binary dut (
    .gray(gray),
    .binary(binary)
);

initial begin
    $monitor("gray = %b, binary = %b", gray, binary);
    
    gray = 4'b0000;
    #10 gray = 4'b0001;
    #10 gray = 4'b0011;
    #10 gray = 4'b0010;
    #10 gray = 4'b0110;
    #10 gray = 4'b0111;
    #10 gray = 4'b0101;
    #10 gray = 4'b0100;
    #10 gray = 4'b1100;
    #10 gray = 4'b1101;
    #10 gray = 4'b1111;
    #10 gray = 4'b1110;
    #10 gray = 4'b1010;
    #10 gray = 4'b1011;
    #10 gray = 4'b1001;
    #10 gray = 4'b1000;
    #10 $finish;
end

endmodule

在testbench文件中，我们通过输入不同的格雷码，测试输出是否正确。