格雷码转二进制verilog程序和testbench文件编写

以下是格雷码转二进制的Verilog程序和testbench文件：

Verilog程序：

module gray_to_binary(
    input [3:0] gray,
    output reg [3:0] binary
    );
    
    always @ (gray) begin
        binary[3] = gray[3];
        binary[2] = binary[3] ^ gray[2];
        binary[1] = binary[2] ^ gray[1];
        binary[0] = binary[1] ^ gray[0];
    end
    
endmodule

testbench文件：

module gray_to_binary_tb;

    reg [3:0] gray;
    wire [3:0] binary;

    gray_to_binary dut(.gray(gray), .binary(binary));

    initial begin
        $monitor("Gray: %b -> Binary: %b", gray, binary);
        gray = 4'b0000;
        #10;
        gray = 4'b0001;
        #10;
        gray = 4'b0011;
        #10;
        gray = 4'b0010;
        #10;
        gray = 4'b0110;
        #10;
        gray = 4'b0111;
        #10;
        gray = 4'b0101;
        #10;
        gray = 4'b0100;
        #10;
        gray = 4'b1100;
        #10;
        gray = 4'b1101;
        #10;
        gray = 4'b1111;
        #10;
        gray = 4'b1110;
        #10;
        gray = 4'b1010;
        #10;
        gray = 4'b1011;
        #10;
        gray = 4'b1001;
        #10;
        gray = 4'b1000;
        #10;
        $finish;
    end

endmodule

在testbench文件中，我们为输入gray信号指定了一些测试值，并在每个测试值后等待10个时钟周期。在这个等待时间内，Verilog模拟器会计算输出binary信号，并在$monitor语句中打印出gray和binary信号的值。最后，我们使用$finish语句结束仿真。