module inner_submod { input logic [9:-1][2:0] sub_input, output logic [9:-1][2:0] sub_output, }; assign sub_output = sub_input +1; endmodule module test_top; typedef struct packed { logic [9:-1][2:0] a; } ST1; typedef struct { ST1 st1; ST1 st2[2:0]; } ST2; inner_submod submod1 { .sub_input(st2.st2[0].a) .sub_output(st2.st2[0].a) }; inner_submod submod2 { .sub_input(st2.st2[0].a) .sub_output(st2.st2[0].a) }; inner_submod submod3 { .sub_input(st2.st2[1].a) .sub_output(st2.st2[1].a) }; initial begin ST2 st2; st2 = '{2'b01, '{3'b1, 3'b0, 12'b1}}; $display("st2:%s",st2); end endmodule this piece of system verilog code, when compiled by vcs, it reports Error-[SE] Syntax error Following verilog source has syntax error : "sc_assignment_pattern_041.sv", 12: token is '{' module inner_submod { how should I modify the code so that it can be compiled successully by vcs? thanks a lot

There are a few syntax errors in the provided code. Here is the corrected code:

module inner_submod (
    input logic [9:-1][2:0] sub_input,
    output logic [9:-1][2:0] sub_output
);
assign sub_output = sub_input + 1;
endmodule

module test_top;

typedef struct packed {
    logic [9:-1][2:0] a;
} ST1;

typedef struct {
    ST1 st1;
    ST1 st2[2:0];
} ST2;

ST2 st2 = '{st1: {a: '{3'b1, 3'b0, 12'b1}}, st2: '{ '{a: '{3'b1, 3'b0, 12'b1}}, '{a: '{3'b1, 3'b0, 12'b1}}, '{a: '{3'b1, 3'b0, 12'b1}} }};

inner_submod submod1 (
    .sub_input(st2.st2[0].a),
    .sub_output(st2.st2[0].a)
);

inner_submod submod2 (
    .sub_input(st2.st2[0].a),
    .sub_output(st2.st2[0].a)
);

inner_submod submod3 (
    .sub_input(st2.st2[1].a),
    .sub_output(st2.st2[1].a)
);

initial begin
    $display("st2:%s",st2);
end

endmodule

The main changes are:

- The `inner_submod` module now has parentheses around the input and output ports.
- The `st2` variable is now defined in-line with the struct field names and array indices specified explicitly.
- The submodule instantiations now have parentheses around the port connections.