module inner_submod； input logic [9:-1][2:0] sub_input; output logic [9:-1][2:0] sub_output; assign sub_output = sub_input + 1; inner_submod submod1 { .sub_input(st2.st2[0].a), .sub_output(st2.st2[0].a) }; inner_submod submod2 { .sub_input(st2.st2[0].a), .sub_output(st2.st2[0].a) }; inner_submod submod3 { .sub_input(st2.st2[1].a), .sub_output(st2.st2[1].a) }; endmodule module test_top; typedef struct packed { logic [9:-1][2:0] a; } ST1; typedef packed struct { ST1 st1; ST1 st2[2:0]; } ST2; initial begin ST2 st2 = '{ 2'b01, {3'b1, 3'b0, 12'b1} }; $display("st2:%s", st2); end endmodule when compiled by vcs, it reports Error-[UTOPN] Unknown type or port name The type name 'inner_submod' is unknown, or the identifier 'submod1' has not been listed as a port, or the declaration might represent an instance missing parentheses. "sc_assignment_pattern_041.sv',20 Source info: inner_submod submod1{ Error-[SE] Syntax error Following verilog source has syntax error: "sc_assignment_pattern_041.sv", 20 how should I fix these 2 errors? thanks a lot

There are a few issues with the code that need to be fixed. Firstly, in the definition of the `inner_submod` module, the semicolon after the module name should be removed. Secondly, the module instances `submod1`, `submod2`, and `submod3` should be declared within the `test_top` module using the `instance` keyword and parentheses. Lastly, the `st2` signal is not declared within the `test_top` module, so it needs to be declared before it is used. Here's the corrected code:

module inner_submod (
    input logic [9:-1][2:0] sub_input,
    output logic [9:-1][2:0] sub_output
);
    assign sub_output = sub_input + 1;
endmodule

module test_top;
    typedef struct packed {
        logic [9:-1][2:0] a;
    } ST1;

    typedef packed struct {
        ST1 st1;
        ST1 st2[2:0];
    } ST2;

    ST2 st2 = '{ 2'b01, {3'b1, 3'b0, 12'b1} };

    inner_submod submod1 (
        .sub_input(st2.st2[0].a),
        .sub_output(st2.st2[0].a)
    );

    inner_submod submod2 (
        .sub_input(st2.st2[0].a),
        .sub_output(st2.st2[0].a)
    );

    inner_submod submod3 (
        .sub_input(st2.st2[1].a),
        .sub_output(st2.st2[1].a)
    );
endmodule

This code should compile without errors.