module inner_submod { input logic [9:-1][2:0] sub_input, output logic [9:-1][2:0] sub_output, }; assign sub_output = sub_input +1; endmodule module test_top; typedef struct packed { logic [9:-1][2:0] a; } ST1; typedef struct { ST1 st1; ST1 st2[2:0]; } ST2; inner_submod submod1 { .sub_input(st2.st2[0].a) .sub_output(st2.st2[0].a) }; inner_submod submod2 { .sub_input(st2.st2[0].a) .sub_output(st2.st2[0].a) }; inner_submod submod3 { .sub_input(st2.st2[1].a) .sub_output(st2.st2[1].a) }; initial begin ST2 st2; st2 = '{2'b01, '{3'b1, 3'b0, 12'b1}}; $display("st2:%s",st2); end endmodule this piece of system verilog code, when compiled by vcs, it reports Error-[SE] Syntax error Following verilog source has syntax error : "sc_assignment_pattern_041.sv", 12: token is '{' module inner_submod { how should I modify the code so that it can be compiled successully by vcs? thanks a lot

There are a few errors in the code that need to be fixed before it can be compiled successfully:

1. In the typedef for ST1, the keyword "packed" should be lowercase.
2. In the typedef for ST2, the keyword "packed" should be added before the struct keyword.
3. In the instantiation of submod1 and submod2, the output should be assigned to st2.st2[0].a instead of st2.st2[1].a.
4. In the instantiation of submod3, the input should be assigned to st2.st2[1].a instead of st2.st2[0].a.
5. In the initial block, the concatenation syntax for initializing st2 should be changed from '{2'b01, '{3'b1, 3'b0, 12'b1}}' to '{ {2'b01}, {3'b1, 3'b0, 12'b1} }'.

Here is the corrected code:

module inner_submod {
    input logic [9:-1][2:0] sub_input;
    output logic [9:-1][2:0] sub_output;
    assign sub_output = sub_input + 1;
}

module test_top;
    typedef struct packed {
        logic [9:-1][2:0] a;
    } ST1;

    typedef packed struct {
        ST1 st1;
        ST1 st2[2:0];
    } ST2;

    inner_submod submod1 {
        .sub_input(st2.st2[0].a),
        .sub_output(st2.st2[0].a)
    };

    inner_submod submod2 {
        .sub_input(st2.st2[0].a),
        .sub_output(st2.st2[0].a)
    };

    inner_submod submod3 {
        .sub_input(st2.st2[1].a),
        .sub_output(st2.st2[1].a)
    };

    initial begin
        ST2 st2 = '{ {2'b01}, {{3'b1, 3'b0, 12'b1}} };
        $display("st2:%s", st2);
    end
endmodule