sure. the piece of system verilog code is as below: module inner_submod ( input logic [9:-1][2:0] sub_input, output logic [9:-1][2:0] sub_output ); assign sub_output = sub_input + 1; endmodule module test_top; typedef struct packed { logic [9:-1][2:0] a; } ST1; typedef struct { ST1 st1; ST1 st2[2:0]; } ST2; ST2 st2 = '{st1: {a: '{3'b1, 3'b0, 12'b1}}, st2: '{ '{a: '{3'b1, 3'b0, 12'b1}}, '{a: '{3'b1, 3'b0, 12'b1}}, '{a: '{3'b1, 3'b0, 12'b1}} }}; inner_submod submod1 ( .sub_input(st2.st2[0].a), .sub_output(st2.st2[0].a) ); inner_submod submod2 ( .sub_input(st2.st2[0].a), .sub_output(st2.st2[0].a) ); inner_submod submod3 ( .sub_input(st2.st2[1].a), .sub_output(st2.st2[1].a) ); initial begin $display("st2:%s",st2); end and the error reported by vcs is: Error-[SE] Syntax error Following verilog source has syntax error : "sc_assignment_pattern_041.sv", 12: token is '{' module inner_submod {

The syntax error is caused by the way you are initializing the ST2 struct. Instead of using the '{...}' syntax, you should use the '{...} with {...} with {...}' syntax to initialize nested structs. Here is the modified code:

module inner_submod (
    input logic [9:-1][2:0] sub_input,
    output logic [9:-1][2:0] sub_output
);

assign sub_output = sub_input + 1;

endmodule

module test_top;

typedef struct packed {
    logic [9:-1][2:0] a;
} ST1;

typedef struct {
    ST1 st1;
    ST1 st2[2:0];
} ST2;

ST2 st2 = '{st1: {a: '{3'b1, 3'b0, 12'b1}}, st2: '{ '{a: '{3'b1, 3'b0, 12'b1}} with 
                                               '{a: '{3'b1, 3'b0, 12'b1}} with 
                                               '{a: '{3'b1, 3'b0, 12'b1}} }}';

inner_submod submod1 (
    .sub_input(st2.st2[0].a),
    .sub_output(st2.st2[0].a)
);

inner_submod submod2 (
    .sub_input(st2.st2[0].a),
    .sub_output(st2.st2[0].a)
);

inner_submod submod3 (
    .sub_input(st2.st2[1].a),
    .sub_output(st2.st2[1].a)
);

initial begin
    $display("st2:%s",st2);
end

endmodule

This should resolve the syntax error reported by vcs.