Verilog语言设计一个“1001"串行数据检测器。输入输出如下: 输入x:000 101 010 010 011 101 001 110 101输出y:000 000 000 010 010 000 001 000 000程序代码及测试文件代码

以下是Verilog代码：

module serial_detector(
    input clk, // 时钟信号
    input reset, // 复位信号
    input data_in, // 输入数据
    output reg data_out // 输出数据
);

reg [3:0] data_reg; // 4位寄存器，存储上一个数据
reg [1:0] state; // 状态机状态

parameter S0 = 2'b00; // 状态0
parameter S1 = 2'b01; // 状态1
parameter S2 = 2'b10; // 状态2
parameter S3 = 2'b11; // 状态3

always @(posedge clk) begin
    if(reset) begin
        data_reg <= 4'b0000;
        state <= S0;
        data_out <= 1'b0;
    end
    else begin
        case(state)
            S0: begin
                if(data_in == 1'b1) begin
                    state <= S1;
                end
            end
            S1: begin
                if(data_in == 1'b0) begin
                    state <= S2;
                end
                else begin
                    state <= S0;
                end
            end
            S2: begin
                if(data_in == 1'b0) begin
                    state <= S3;
                end
                else begin
                    state <= S0;
                end
            end
            S3: begin
                if(data_in == 1'b1) begin
                    state <= S0;
                    data_out <= 1'b1;
                end
                else begin
                    state <= S0;
                end
            end
        endcase

        if(state == S0) begin
            data_reg <= {data_reg[2:0], data_in};
        end
    end
end

endmodule

以下是测试文件代码：

module serial_detector_test();

reg clk;
reg reset;
reg data_in;
wire data_out;

serial_detector dut(
    .clk(clk),
    .reset(reset),
    .data_in(data_in),
    .data_out(data_out)
);

initial begin
    clk = 0;
    reset = 1;
    data_in = 0;
    #10 reset = 0;
    #10 data_in = 0;
    #10 data_in = 0;
    #10 data_in = 1;
    #10 data_in = 0;
    #10 data_in = 1;
    #10 data_in = 0;
    #10 data_in = 1;
    #10 data_in = 0;
    #10 data_in = 0;
    #10 data_in = 1;
    #10 data_in = 0;
    #10 data_in = 0;
    #10 data_in = 1;
    #10 data_in = 1;
    #10 data_in = 0;
    #10 data_in = 0;
    #10 data_in = 1;
    #10 data_in = 1;
    #10 data_in = 0;
    #10 data_in = 1;
    #10 data_in = 0;
    #10 data_in = 0;
    #10 $finish;
end

always #5 clk = ~clk;

endmodule

测试文件中，我们模拟了一个时钟信号和输入数据，并将其输入到了设计的串行数据检测器中，然后观察输出结果，验证设计的正确性。