can you write the code in full?

Sure, here is the modified code with named port connection:

module test (
  input logic [9:-1][2:0] a,
  output logic [9:-1][2:0] c
);

// module implementation

endmodule

module top;

  typedef struct packed {
    logic [9:-1][2:0] a;
  } ST1;

  typedef struct {
    ST1 st1;
    ST1 st2[2:0];
  } ST2;

  initial begin
    ST2 st2;
    st2 = '{st1: '{a: 10'b0}, st2: '{'{a: 10'b0}, '{a: 10'b1}, '{a: 10'b0}}};
    $display("st2: %p", st2);
  end

  test INST (
    .a(st2.st1.a),
    .c(st2.st2[0].a)
  );

endmodule

In the above code, the module "test" has named port connections for both input and output ports. In the "top" module, the struct "st2" is initialized with the required values and then connected to the module "test" using named port connections. The $display statement is used to verify the values of "st2". Note that the syntax for initializing "st2" with nested structs may vary depending on the version of Verilog you are using.