verilog语言实现74160十进制计数器

Verilog代码如下：

module counter (
  input clk,
  input rst,
  output reg [3:0] count_out
);

  always @(posedge clk or posedge rst) begin
    if (rst) begin
      count_out <= 0;
    end else begin
      case (count_out)
        4'b0000: count_out <= 4'b0001;
        4'b0001: count_out <= 4'b0010;
        4'b0010: count_out <= 4'b0011;
        4'b0011: count_out <= 4'b0100;
        4'b0100: count_out <= 4'b0101;
        4'b0101: count_out <= 4'b0110;
        4'b0110: count_out <= 4'b0111;
        4'b0111: count_out <= 4'b1000;
        4'b1000: count_out <= 4'b1001;
        4'b1001: count_out <= 4'b0000;
      endcase
    end
  end

endmodule

这个模块实现了一个4位十进制计数器，当clk为正极沿触发时，计数器会递增一位，当rst为正极沿触发时，计数器会被清零。计数器的最大值为9，所以当计数器的值达到9时，下一个值会再次从0开始计数。