多功能数字钟verilog
时间: 2023-05-29 09:04:33 浏览: 163
module multifunctional_clock(
input clk, //时钟信号
input rst, //复位信号
input [1:0] mode, //模式选择信号
output reg [6:0] seg, //七段数码管显示信号
output reg [3:0] an //数码管位选信号
);
reg [3:0] cnt = 0; //计数器,用于控制数码管位选
reg [26:0] count = 0; //计数器,用于计时
reg [1:0] blink_cnt = 0; //计数器,用于闪烁
always @(posedge clk, posedge rst) begin
if (rst) begin
count <= 0;
seg <= 7'b0000000;
an <= 4'b1110;
cnt <= 0;
blink_cnt <= 0;
end else begin
case (mode)
2'b00: begin //时钟模式
if (count == 50000000) begin //计时器到达1s
count <= 0;
if (seg[6:4] == 3'b001) begin //小时部分的个位数为9
if (seg[3:0] == 4'b1001) //小时部分的十位数为2
seg <= 7'b0000000; //时钟归零
else
seg <= {2'b10, seg[3:0]+1}; //小时部分的十位数加1
end else if (seg[3:0] == 4'b1001) begin //小时部分的十位数为9
seg <= {seg[6:4]+1, 4'b0000}; //小时部分的十位数归零,个位数加1
end else begin
seg <= {seg[6:4], seg[3:0]+1}; //小时部分的个位数加1
end
end else begin
count <= count + 1;
end
end
2'b01: begin //计时器模式
if (count == 50000000) begin //计时器到达1s
count <= 0;
if (seg[6:4] == 3'b001) begin //分钟部分的个位数为9
if (seg[3:0] == 4'b1001) begin //分钟部分的十位数为5
if (seg[6:4] == 3'b001 && seg[3:0] == 4'b1001) //计时器到达60min
seg <= 7'b0000000; //计时器归零
else
seg <= {2'b10, seg[3:0]+1}; //分钟部分的十位数加1
end else begin
seg <= {seg[6:4], seg[3:0]+1}; //分钟部分的个位数加1
end
end else begin
seg <= {seg[6:4], seg[3:0]+1}; //分钟部分的个位数加1
end
end else begin
count <= count + 1;
end
end
2'b10: begin //设置模式
blink_cnt <= blink_cnt + 1; //闪烁计数器加1
if (blink_cnt == 25000000) begin //闪烁计数器到达0.5s
blink_cnt <= 0;
seg <= ~seg; //数码管取反,实现闪烁效果
end
end
2'b11: begin //停止模式
seg <= 7'b0000000;
an <= 4'b1110;
cnt <= 0;
end
endcase
if (cnt == 4'b1000) begin //数码管位选计数器到达8
cnt <= 0;
an <= {an[2:0], an[3]}; //数码管位选信号循环移位
end else begin
cnt <= cnt + 1;
end
end
end
endmodule