多功能数字时钟 verilog 搜索具有计时，秒表，时钟三个功能的文章

以下是一个具有计时、秒表和时钟功能的Verilog数字时钟的代码示例。该代码可在FPGA板上运行。

module clock(
    input clk,
    input rst,
    output reg [3:0] seg1,
    output reg [3:0] seg2,
    output reg [3:0] seg3,
    output reg [3:0] seg4
);

reg [26:0] count;
reg [3:0] ones;
reg [3:0] tens;
reg [3:0] h_ones;
reg [3:0] h_tens;
reg [3:0] m_ones;
reg [3:0] m_tens;
reg [3:0] s_ones;
reg [3:0] s_tens;
reg [1:0] mode;

always @(posedge clk) begin
    if(rst) begin
        count <= 0;
        ones <= 0;
        tens <= 0;
        h_ones <= 0;
        h_tens <= 0;
        m_ones <= 0;
        m_tens <= 0;
        s_ones <= 0;
        s_tens <= 0;
        mode <= 0;
    end else begin
        count <= count + 1;
        if(count == 50000000) begin
            count <= 0;
            ones <= ones + 1;
            if(ones == 10) begin
                ones <= 0;
                tens <= tens + 1;
                if(tens == 6) begin
                    tens <= 0;
                    h_ones <= h_ones + 1;
                    if(h_ones == 10) begin
                        h_ones <= 0;
                        h_tens <= h_tens + 1;
                        if(h_tens == 10) begin
                            h_tens <= 0;
                        end
                    end
                end
            end
        end
    end
end

always @(posedge clk) begin
    if(rst) begin
        ones <= 0;
        tens <= 0;
        h_ones <= 0;
        h_tens <= 0;
        m_ones <= 0;
        m_tens <= 0;
        s_ones <= 0;
        s_tens <= 0;
        mode <= 0;
    end else begin
        if(mode == 0) begin
            s_ones <= ones;
            s_tens <= tens;
            m_ones <= h_ones;
            m_tens <= h_tens;
        end else if(mode == 1) begin
            s_ones <= ones;
            s_tens <= tens;
        end else if(mode == 2) begin
            m_ones <= count % 10;
            m_tens <= count / 10 % 6;
            s_ones <= count / 100 % 10;
            s_tens <= count / 1000 % 6;
        end
    end
end

always @(posedge clk) begin
    if(rst) begin
        seg1 <= 4'b0000;
        seg2 <= 4'b0000;
        seg3 <= 4'b0000;
        seg4 <= 4'b0000;
    end else begin
        case(mode)
            0: begin
                seg1 <= 4'b1111;
                seg2 <= {4{tens[3]}};
                seg3 <= {4{ones[3]}};
                seg4 <= 4'b1110;
            end
            1: begin
                seg1 <= {4{m_tens[3]}};
                seg2 <= {4{m_ones[3]}};
                seg3 <= {4{s_tens[3]}};
                seg4 <= {4{s_ones[3]}};
            end
            2: begin
                seg1 <= {4{m_tens[3]}};
                seg2 <= {4{m_ones[3]}};
                seg3 <= {4{s_tens[3]}};
                seg4 <= {4{s_ones[3]}};
            end
        endcase
    end
end

always @(posedge clk) begin
    if(rst) begin
        mode <= 0;
    end else begin
        if(mode == 0 && ones == 3 && tens == 5 && h_ones == 2 && h_tens == 4) begin
            mode <= mode + 1;
        end else if(mode == 1 && ones == 0 && tens == 0) begin
            mode <= mode + 1;
        end else if(mode == 2 && count == 60000000) begin
            mode <= 0;
        end
    end
end

endmodule

该代码使用时钟信号和复位信号作为输入，并输出四个七段数码管的信号。代码包含计数器，用于计时，并将结果转换为可显示的数字。此外，代码还包含三个模式，用于切换时钟、秒表和计时器功能。

在模式0下，数字时钟显示当前时间，包括小时和分钟。在模式1下，数字时钟将显示已经过去的时间，包括小时，分钟和秒。在模式2下，数字时钟将显示计时器的值，包括分钟和秒。在每个模式之间切换时，需要按下按钮。

请注意，此代码示例可能需要针对您的FPGA板进行修改，以便正确显示数字。