方波信号发生器的testbench

以下是一个方波信号发生器的testbench的示例代码，其中包括了一个时钟模块和一个方波信号发生器模块。在testbench中，我们使用了高级testbenches技术，即每10个时钟周期只采样一次相关信号，以保证足够的仿真速度。

`timescale 1ns/1ns

module clk_gen
(
    input clk_in,
    output reg clk_out
);

parameter DIVIDE_FACTOR = 2;

reg [DIVIDE_FACTOR-1:0] counter;

always @(posedge clk_in)
begin
    if (counter == DIVIDE_FACTOR-1)
    begin
        counter <= 0;
        clk_out <= ~clk_out;
    end
    else
        counter <= counter + 1;
end

endmodule

module square_wave_gen
(
    input clk,
    input rst,
    output reg square_wave
);

parameter PERIOD = 100;
reg [PERIOD-1:0] counter;

always @(posedge clk or posedge rst)
begin
    if (rst)
    begin
        counter <= 0;
        square_wave <= 0;
    end
    else if (counter == PERIOD/2-1)
    begin
        counter <= 0;
        square_wave <= ~square_wave;
    end
    else
        counter <= counter + 1;
end

endmodule

module tb_square_wave_gen;

reg clk;
reg rst;
wire square_wave;

initial
begin
    clk = 0;
    forever #5 clk = ~clk;
end

initial
begin
    rst = 1;
    #10 rst = 0;
end

clk_gen #(.DIVIDE_FACTOR(2)) clk_inst (.clk_in(clk), .clk_out(clk));

square_wave_gen square_wave_inst (.clk(clk), .rst(rst), .square_wave(square_wave));

always @(posedge clk)
begin
    if ($time % 100 == 0)
        $display("Time = %0t, square_wave = %b", $time, square_wave);
end

endmodule