kinside <= unsigned(resize(signed(sp), 16)) * unsigned(resize(signed(DISTANCE_PER_CLK), 16)) / to_unsigned(3600, 16);仍有Error (10344): VHDL expression error at taxi.vhd(298): expression has 32 elements, but must have 16 elements的问题出现

这个错误提示表明在你的 VHDL 代码中，有一个表达式包含了 32 个元素，但是根据代码逻辑，它应该只有 16 个元素。这通常是由于类型不匹配或者运算符优先级不正确等原因引起的。

在这个具体的表达式中，你需要确保 signed(sp) 和 signed(DISTANCE_PER_CLK) 的值都是 16 位的，并且 to_unsigned(3600, 16) 返回的也是 16 位的无符号数。如果其中任何一个值的长度不正确，那么在进行乘法和除法运算时就会出现错误。

另外，你可以尝试使用括号来明确运算的优先级，例如：

kinside <= unsigned(resize(signed(sp), 16)) * (unsigned(resize(signed(DISTANCE_PER_CLK), 16)) / to_unsigned(3600, 16));

这样可以确保先进行除法运算，再进行乘法运算，避免出现优先级错误。

相关问题

把下面代码改成VHDL的格式”module Calibration( input i_clk , input i_rst , input signed[9:0] i_an , input signed[9:0] i_bn , input i_sample_valid, input [9:0] i_sample_ADC , output o_T_valid , output signed[13:0] o_T ); reg signed[13:0] r_T = 14'sd0; reg r_T_valid = 1'b0 ; wire signed[10:0] w_sample_ADC = {1'b0,i_sample_ADC}; always @(posedge i_clk)begin if(i_rst)begin r_T <= 12'sd0; r_T_valid <= 1'b0; end else if(i_sample_valid)begin r_T <= w_sample_ADC*i_an + i_bn; r_T_valid <= 1'b1; end else r_T_valid <= 1'b0; end assign o_T_valid = r_T_valid; assign o_T = r_T[13:4] ; endmodule“

以下是将给定的代码转换为VHDL格式的结果：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Calibration is
    port (
        i_clk           : in    std_logic;
        i_rst           : in    std_logic;
        i_an            : in    signed(9 downto 0);
        i_bn            : in    signed(9 downto 0);
        i_sample_valid  : in    std_logic;
        i_sample_ADC    : in    unsigned(9 downto 0);
        o_T_valid       : out   std_logic;
        o_T             : out   signed(13 downto 0)
    );
end entity Calibration;

architecture Behavioral of Calibration is
    signal w_sample_ADC : signed(10 downto 0);
    signal r_T          : signed(13 downto 0) := to_signed(0, 14);
    signal r_T_valid    : std_logic := '0';
begin
    w_sample_ADC <= signed('0' & i_sample_ADC);

    process (i_clk)
    begin
        if rising_edge(i_clk) then
            if i_rst = '1' then
                r_T <= to_signed(0, 14);
                r_T_valid <= '0';
            elsif i_sample_valid = '1' then
                r_T <= w_sample_ADC * i_an + i_bn;
                r_T_valid <= '1';
            else
                r_T_valid <= '0';
            end if;
        end if;
    end process;

    o_T_valid <= r_T_valid;
    o_T <= r_T(13 downto 4);
end architecture Behavioral;

需要注意的一些事项：

- 使用 `ieee.numeric_std.all` 包来支持 signed 和 unsigned 数据类型。
- 由于输入信号 `i_sample_ADC` 是 unsigned 类型，需要使用 `signed` 转换为 signed 类型，并在 signals 和 variables 中使用 signed 数据类型。
- 由于输出信号 `o_T` 是 signed 类型，需要在 port 中声明 signed 类型，并在 assign 语句中使用 signed 类型。
- 对于 `r_T` 和 `r_T_valid`，使用 signal 声明，因为在 process 中需要对它们进行赋值。
- 使用 `to_signed` 函数来将十进制数字转换为 signed 类型。
- 使用 `rising_edge` 函数来检测时钟上升沿的信号变化。

讲下面这个Verilog文件转化为VHDL文件“module Serial_output( input i_clk , input i_rst , input i_T_valid , input signed[9:0] i_T , input [3 :0] i_Device_ID , output reg o_Serial_data ); reg Frame_valid = 1'd0 ; reg [13:0] Frame = 13'd0; always @(posedge i_clk)begin if(i_rst == 1'b1)begin Frame_valid <= 1'd0 ; Frame <= 13'd0; end else if(i_T_valid)begin Frame_valid <= 1'b1 ; Frame <= {i_Device_ID,i_T}; end else Frame_valid <= 1'd0 ; end reg [2:0] s_Frame_valid = 3'd0; always @(posedge i_clk)begin s_Frame_valid <= {s_Frame_valid[1:0],Frame_valid}; end reg [4:0] r_bit_cnt = 5'd0; always @(posedge i_clk)begin if(i_rst == 1'b1) r_bit_cnt <= 5'd0; else if(s_Frame_valid[2]) r_bit_cnt <= 5'd0; else if(r_bit_cnt >= 5'd13) r_bit_cnt <= r_bit_cnt; else r_bit_cnt <= r_bit_cnt + 1'b1; end always @(*)begin case (r_bit_cnt) 5'd0 :o_Serial_data <= Frame[13] ; 5'd1 :o_Serial_data <= Frame[12] ; 5'd2 :o_Serial_data <= Frame[11] ; 5'd3 :o_Serial_data <= Frame[10] ; 5'd4 :o_Serial_data <= Frame[9] ; 5'd5 :o_Serial_data <= Frame[8] ; 5'd6 :o_Serial_data <= Frame[7] ; 5'd7 :o_Serial_data <= Frame[6] ; 5'd8 :o_Serial_data <= Frame[5] ; 5'd9 :o_Serial_data <= Frame[4] ; 5'd10 :o_Serial_data <= Frame[3] ; 5'd11 :o_Serial_data <= Frame[2] ; 5'd12 :o_Serial_data <= Frame[1] ; endcase end endmodule”

以下是转化后的VHDL文件：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Serial_output is
    port (
        i_clk         : in  std_logic;
        i_rst         : in  std_logic;
        i_T_valid     : in  std_logic;
        i_T           : in  signed(9 downto 0);
        i_Device_ID   : in  std_logic_vector(3 downto 0);
        o_Serial_data : out std_logic
    );
end entity;

architecture Behavioral of Serial_output is
    signal Frame_valid : std_logic := '0';
    signal Frame       : unsigned(13 downto 0) := (others => '0');
    signal s_Frame_valid : unsigned(2 downto 0) := (others => '0');
    signal r_bit_cnt : unsigned(4 downto 0) := (others => '0');
begin

    process (i_clk)
    begin
        if rising_edge(i_clk) then
            if i_rst = '1' then
                Frame_valid <= '0';
                Frame <= (others => '0');
            elsif i_T_valid = '1' then
                Frame_valid <= '1';
                Frame <= unsigned(i_Device_ID & i_T);
            else
                Frame_valid <= '0';
            end if;
        end if;
    end process;

    process (i_clk)
    begin
        if rising_edge(i_clk) then
            s_Frame_valid <= s_Frame_valid(1 downto 0) & Frame_valid;
        end if;
    end process;

    process (r_bit_cnt)
    begin
        case r_bit_cnt is
            when "00000" =>
                o_Serial_data <= std_logic(Frame(13));
            when "00001" =>
                o_Serial_data <= std_logic(Frame(12));
            when "00010" =>
                o_Serial_data <= std_logic(Frame(11));
            when "00011" =>
                o_Serial_data <= std_logic(Frame(10));
            when "00100" =>
                o_Serial_data <= std_logic(Frame(9));
            when "00101" =>
                o_Serial_data <= std_logic(Frame(8));
            when "00110" =>
                o_Serial_data <= std_logic(Frame(7));
            when "00111" =>
                o_Serial_data <= std_logic(Frame(6));
            when "01000" =>
                o_Serial_data <= std_logic(Frame(5));
            when "01001" =>
                o_Serial_data <= std_logic(Frame(4));
            when "01010" =>
                o_Serial_data <= std_logic(Frame(3));
            when "01011" =>
                o_Serial_data <= std_logic(Frame(2));
            when "01100" =>
                o_Serial_data <= std_logic(Frame(1));
            when others =>
                null;
        end case;
    end process;

    process (i_clk)
    begin
        if rising_edge(i_clk) then
            if i_rst = '1' then
                r_bit_cnt <= (others => '0');
            elsif s_Frame_valid(2) = '1' then
                r_bit_cnt <= (others => '0');
            elsif r_bit_cnt >= 13 then
                r_bit_cnt <= r_bit_cnt;
            else
                r_bit_cnt <= r_bit_cnt + 1;
            end if;
        end if;
    end process;

end architecture;