8线3线优先编码器代码vhdl

8线3线优先编码器是一种数字电路，用于将8个输入线的状态编码为3位二进制代码。这里提供一种可能的VHDL代码实现：

entity priority_encoder is
    port (
        input_0 : in std_logic;
        input_1 : in std_logic;
        input_2 : in std_logic;
        input_3 : in std_logic;
        input_4 : in std_logic;
        input_5 : in std_logic;
        input_6 : in std_logic;
        input_7 : in std_logic;
        output : out std_logic_vector(2 downto 0)
    );
end entity priority_encoder;

architecture behavioral of priority_encoder is
begin
    process (input_0, input_1, input_2, input_3, input_4, input_5, input_6, input_7)
    begin
        case is
            when "00000001" =>
                output <= "000";
            when "00000010" =>
                output <= "001";
            when "00000100" =>
                output <= "010";
            when "00001000" =>
                output <= "011";
            when "00010000" =>
                output <= "100";
            when "00100000" =>
                output <= "101";
            when "01000000" =>
                output <= "110";
            when "10000000" =>
                output <= "111";
            when others =>
                output <= "000";
        end case;
    end process;
end architecture behavioral;

在这个实现中，输入由`input_0`到`input_7`表示，输出是一个3位二进制代码，由`output`表示。根据优先级编码，当有多个输入同时处于高电平时，输出选择最高的那个输入对应的编码。如果所有输入都为低电平，则输出为0。