8-3线优先编码器vhdl

以下是一个简单的 8-3 优先编码器的 VHDL 代码示例：

entity priority_encoder is
    port (
        input_vector : in std_logic_vector(7 downto 0);
        output_vector : out std_logic_vector(2 downto 0)
    );
end entity priority_encoder;

architecture Behavioral of priority_encoder is
begin
    process (input_vector)
    begin
        case input_vector is
            when "00000001" => output_vector <= "000";
            when "00000010" => output_vector <= "001";
            when "00000100" => output_vector <= "010";
            when "00001000" => output_vector <= "011";
            when "00010000" => output_vector <= "100";
            when "00100000" => output_vector <= "101";
            when "01000000" => output_vector <= "110";
            when "10000000" => output_vector <= "111";
            when others => output_vector <= "000"; -- default case
        end case;
    end process;
end architecture Behavioral;

该代码将一个 8 位输入向量转换为一个 3 位输出向量。输入向量的每个位表示一个优先级别，最高的优先级别在最左边，最低的在最右边。输出向量的每个位表示对应输入向量中最高优先级别的位所在的位置。如果输入向量的所有位都是 0，那么输出向量将被置为 000。