用Verilog 描述能够产生“1101000101”序列信号的序列信号产生器,写出代码。
时间: 2023-05-21 16:00:49 浏览: 74
module seq_gen(
input clk,
output reg out
);
reg [9:0] counter;
always @(posedge clk) begin
case(counter)
0: out <= 1'b1;
1: out <= 1'b1;
2: out <= 1'b0;
3: out <= 1'b1;
4: out <= 1'b0;
5: out <= 1'b0;
6: out <= 1'b0;
7: out <= 1'b1;
8: out <= 1'b0;
9: out <= 1'b1;
endcase
counter <= counter + 1;
end
endmodule
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用Verilog描述能够产生1101000101序列信号的序列信号产生器,写出代码
module seq_gen(
input clk,
input rst,
output reg out
);
reg [9:0] count;
always @(posedge clk or negedge rst)
begin
if (rst == 0) begin
out <= 0;
count <= 0;
end
else begin
case(count)
4'd0: out <= 1;
4'd1: out <= 1;
4'd2: out <= 0;
4'd3: out <= 1;
4'd4: out <= 0;
4'd5: out <= 0;
4'd6: out <= 0;
4'd7: out <= 1;
4'd8: out <= 0;
4'd9: out <= 1;
endcase
count <= count + 1;
end
end
endmodule
用Verilog 描述能够产生“1101000101序列信号的序列信号产生器,写出代码
module seq_gen(
input clk,
output reg out
);
reg [9:0] count;
always @(posedge clk) begin
if (count == 10'b1101000101) begin
count <= 0;
out <= ~out;
end else begin
count <= {count[8:0], count[9]};
end
end
endmodule
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