LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY QIANGDAQI IS PORT(CLK,CLK2,S0,S1,S2,S3,S4,S5,S6,STOP,RST:IN STD_LOGIC; N,K,Q_OUT:OUT STD_LOGIC; M:OUT STD_LOGIC_VECTOR(1 DOWNTO 0); A,B,C,D,E,F,G:OUT STD_LOGIC); END QIANGDAQI; ARCHITECTURE BHV OF QIANGDAQI IS COMPONENT QDJB IS PORT(CLK2,RST:IN STD_LOGIC; S0,S1,S2,S3,S4,S5:IN STD_LOGIC; TMP:OUT STD_LOGIC; STATES:OUT STD_LOGIC_VECTOR(5 DOWNTO 0)); END COMPONENT; COMPONENT JS IS PORT(CLK,RST,S,STOP:IN STD_LOGIC; WARN:OUT STD_LOGIC; TA,TB:BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0)); END COMPONENT; COMPONENT SJXZ IS PORT(CLK2,RST:IN STD_LOGIC; S:OUT STD_LOGIC_VECTOR(1 DOWNTO 0); A,B,C:IN STD_LOGIC_VECTOR(3 DOWNTO 0); Y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT; COMPONENT YMQ IS PORT(AIN4: IN STD_LOGIC_VECTOR (3 DOWNTO 0); DOUT7: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END COMPONENT; COMPONENT ALARM IS PORT(CLK,I:IN STD_LOGIC; Q:OUT STD_LOGIC); END COMPONENT; SIGNAL STATES_OUT,TA_OUT,TB_OUT,Y_OUT:Std_LOGIC_VECTOR(6 downto 0); SIGNAL LEDOUT:STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL W:STD_LOGIC; BEGIN A<=LEDOUT(6); B<=LEDOUT(5); C<=LEDOUT(4); D<=LEDOUT(3); E<=LEDOUT(2); F<=LEDOUT(1); G<=LEDOUT(0); U1:QDJB PORT MAP(CLK2,RST,S0,S1,S2,S3,s4,s5,TMP=>K,STATES=>STATES_OUT); U2:JS PORT MAP(CLK,RST,S,STOP,WARN=>N,TA=>TA_OUT,TB=>TB_OUT); U3:SJXZPORTMAP(CLK2=>CLK2,RST=>RST,S=>M,A=>STATES_OUT,B=>TA_OUT, C=>TB_OUT,Y=>Y_OUT); U4:YMQ PORT MAP(AIN4=>Y_OUT,DOUT7=>LEDOUT); U5:ALARM PORT MAP(CLK2,S,Q_OUT); END BHV;
时间: 2024-04-21 08:29:32 浏览: 138
这段代码看起来还是有一些错误,下面是我发现的几个问题:
1.在组件U3的实例化中,SJXZ后面应该有一个空格,应该改为SJXZ PORT MAP,否则代码会编译报错。
2.在组件JS的实例化中,TA和TB的类型应该为BUFFER,而不是BUFFER STD_LOGIC_VECTOR。
3.在组件ALARM的实例化中,输入参数应该是CLK和I,而不是CLK2和S。
下面是修改后的代码,你可以尝试运行一下看看是否能够成功编译:
```
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY QIANGDAQI IS
PORT(CLK,CLK2,S0,S1,S2,S3,S4,S5,S6,STOP,RST:IN STD_LOGIC;
N,K,Q_OUT:OUT STD_LOGIC;
M:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
A,B,C,D,E,F,G:OUT STD_LOGIC);
END QIANGDAQI;
ARCHITECTURE BHV OF QIANGDAQI IS
COMPONENT QDJB IS
PORT(CLK2,RST:IN STD_LOGIC;
S0,S1,S2,S3,S4,S5:IN STD_LOGIC;
TMP:OUT STD_LOGIC;
STATES:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END COMPONENT;
COMPONENT JS IS
PORT(CLK,RST,S,STOP:IN STD_LOGIC;
WARN:OUT STD_LOGIC;
TA,TB:BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0));
END COMPONENT;
COMPONENT SJXZ IS
PORT(CLK2,RST:IN STD_LOGIC;
S:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
A,B,C:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT YMQ IS
PORT(AIN4: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
DOUT7: OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
END COMPONENT;
COMPONENT ALARM IS
PORT(CLK,I:IN STD_LOGIC;
Q:OUT STD_LOGIC);
END COMPONENT;
SIGNAL STATES_OUT,TA_OUT,TB_OUT,Y_OUT:STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL LEDOUT:STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL W:STD_LOGIC;
BEGIN
A<=LEDOUT(6);
B<=LEDOUT(5);
C<=LEDOUT(4);
D<=LEDOUT(3);
E<=LEDOUT(2);
F<=LEDOUT(1);
G<=LEDOUT(0);
U1:QDJB PORT MAP(CLK2,RST,S0,S1,S2,S3,S4,S5,TMP=>K,STATES=>STATES_OUT);
U2:JS PORT MAP(CLK,RST,S,STOP,WARN=>N,TA=>TA_OUT,TB=>TB_OUT);
U3:SJXZ PORT MAP(CLK2=>CLK2,RST=>RST,S=>M,A=>STATES_OUT,B=>TA_OUT,C=>TB_OUT,Y=>Y_OUT);
U4:YMQ PORT MAP(AIN4=>Y_OUT,DOUT7=>LEDOUT);
U5:ALARM PORT MAP(CLK,I,Q_OUT);
END BHV;
```
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